Primary Total Ionizing Dose Effect Studies on Xilinx SoC Irradiated with 60Co γ Rays

Article Preview

Abstract:

We designed radiation effect experimental system including current measurement section and functional test section for Xilinx Zynq-7010 System on chip (SoC) and performed the Total Ionizing Dose (TID) experiment irradiated by Co60 γ-source on the chip. At the dose rate of 0.04 Gy(Si)/s, the total dose of 1.69 kGy(Si), the current value in the experiment increased first and then decreased. The test board got functional interruption at the gamma dose of 1.69 kGy(Si). The function of the board normalized after room temperature annealing and 70°C high temperature annealing except that the current value decreased by 28% compared to the current before irradiation. The mechanisms for the first TID test results on Xilinx SoC were deduced and discussed.

You might also be interested in these eBooks

Info:

Periodical:

Pages:

252-259

Citation:

Online since:

October 2014

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2014 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

* - Corresponding Author

[1] R. Velazco, R. Ecoffet, F. Faure: How to characterize the problem of SEU in processors & representative errors observed on flight[C]. Washington, DC, USA: IEEE Computer Society, 2005: 303-308.

DOI: 10.1109/iolts.2005.32

Google Scholar

[2] KL. Bedingfield, RD. Leach, MB. Alexander: Spacecraft system failures and anomalies attributed to the natural space environment[M]. National Aeronautics and Space Administration, Marshall Space Flight Center, (1996).

DOI: 10.2514/6.1995-3564

Google Scholar

[3] F. Irom: Guideline for ground radiation testing of microprocessors in the space radiation environment[J]. (2008).

Google Scholar

[4] Information on http: /www. zedboard. org/product/microzed.

Google Scholar

[5] GM. Swift, SM. Guertin, F. Farmanesh, et al: Single-event upset in the PowerPC750 microprocessor[J]. IEEE Transactions on Nuclear Science, 2001, 48 (6): 1822-1627.

DOI: 10.1109/23.983136

Google Scholar

[6] F. Irom, F. Farmanesh, A. Johnston, et al: Single-event upset in commercial silicon-on-insulator PowerPC microprocessors[J]. IEEE Transactions on Nuclear Science, 2002, 49 (6): 3148-3155.

DOI: 10.1109/tns.2002.805441

Google Scholar

[7] F. Irom, F. Farmanesh, CK. Kouba: Single-event upset and scaling trends in new generation of the commercial SOI PowerPC microprocessors[J]. IEEE Transactions on Nuclear Science, 2006, 53 (6): 3563-3568.

DOI: 10.1109/tns.2006.884383

Google Scholar

[8] B. Wie, M. Plante, A. Berkley, et al: Static, Dynamic, and Application-Level SEE Results for a 49-Core RHBD Processor[C]. Washington, DC, USA: IEEE Computer Society, 2013: 1-9.

DOI: 10.1109/redw.2013.6658217

Google Scholar

[9] SM. Guertin, F. Irom: Recent Results for PowerPC Processor and Bridge Chip Testing[C]. Washington, DC, USA: IEEE Computer Society, 2010: 978-986.

DOI: 10.1109/redw.2010.5619489

Google Scholar