A CMOS Input Buffer for High-Resolution A/D Converters with High Sampling Rates

Xing Fa Huang; Rong Bin Hu; Liang Li

doi:10.4028/www.scientific.net/AMM.678.497

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 678A CMOS Input Buffer for High-Resolution A/D...

A CMOS Input Buffer for High-Resolution A/D Converters with High Sampling Rates

Abstract:

With respect to the application of high-speed, high-resolution A/D converter, the design and implementation of a CMOS input buffer is introduced. The buffer features high-speed and high-linearity. Its performances have been verified in a 14-bit 250MSPS pipelined A/D converter which is developed in 0.18um CMOS-based process technology. The simulation shows that the SFDR of the buffer is up to 104dB at an input clock of 250MHz with an input signal of 25MHz.

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Periodical:

Applied Mechanics and Materials (Volume 678)

Pages:

497-500

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.678.497

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Online since:

October 2014

Authors:

Xing Fa Huang*, Rong Bin Hu, Liang Li

Keywords:

A/D Converter, Buffer, High Linearity, High Speed

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* - Corresponding Author

References

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DOI: 10.1109/jssc.2010.2073194

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DOI: 10.1109/jssc.2008.917427

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