Multi-Bit Flip-Flop Replacement Method Optimization and Synthesis Impact

An Jing Wang; Yu Zhuo Fu

doi:10.4028/www.scientific.net/AMM.716-717.1239

Paper Titles

Research on the Mathematical Model Construction and Algorithm of Dynamic Reactive Power Optimization about Distribution Network
p.1221

Realization of Automatic Power Control in HVDC Control and Protection System
p.1226

Design of Voice Communication System Based on the ZigBee Technology for Power Plant
p.1230

Encoding and Decoding Schemes for MIMO System Combined with Convolutional Code
p.1234

Multi-Bit Flip-Flop Replacement Method Optimization and Synthesis Impact
p.1239

Research on Interference Model of Cooperative Cognitive Radio Networks over Rayleigh Fading Channel
p.1244

Realization of Programmable Analog Circuits with Digital Potentiometer
p.1248

Adaptive Algorithm for Anti-Jamming in Broadband Communication
p.1252

Design of Mobile Communication Non Intersymbol Interference System Based on Calman Filter and PID Control
p.1257

HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 716-717Multi-Bit Flip-Flop Replacement Method...

Multi-Bit Flip-Flop Replacement Method Optimization and Synthesis Impact

Abstract:

Recently, Multi-bit flip-flop usage has shown its advantage in dynamic power saving in nowadays commercial electronic design. This paper present a more comprehensive comparison of chip-level synthesis result by using single-bit flip-flop and multi-bit flip-flop standard cell and except for analyzing the power and area benefit from replacement under the maximum speed, this paper give a compromise solution to solve that using multi-bit flip-flop cannot run as the fastest as single-bit with even large area. The trade-off between a multi-bit flip-flop cell driving strength and its area when designing multi-bit standard cell that will greatly influence synthesis result as speed arise are also mentioned. Finally, this research about MBFF further usage improvements may be helpful for designers to know how to take full advantage of multi-bit flip-flops to bring about the wanted benefit.

You might also be interested in these eBooks

Mechanical Engineering and Materials Science

View Preview

Info:

Periodical:

Applied Mechanics and Materials (Volumes 716-717)

Pages:

1239-1243

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.716-717.1239

Citation:

Cite this paper

Online since:

December 2014

Authors:

An Jing Wang*, Yu Zhuo Fu

Keywords:

Area Saving, Multi-Bit Flip-Flop, Physical Synthesis

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] D. Liu and C. Svensson, Power consumption estimation in CMOS VLSI chips, IEEE Solid-State Circuits, vol. 29, no. 6, p.663–670, Jun. (1994).

DOI: 10.1109/4.293111

Google Scholar

[2] Pei-Hsin Ho, Industrail clock design, in Proceedings of the ACM International Symposium on Physical Design(ISPD), 2009, pp.139-140.

Google Scholar

[3] Y. Kretchmer, Using multibit register inference to save area and power, , EE Times Asia, May (2001).

Google Scholar

[4] R. P. Pokala, R. A. Feretich, and R. W. McGuffin, Physical synthesis for performance optimization, in Proc. IEEE Int. ASIC Conf. Exhibit. Sep. 1992, p.34–37.

DOI: 10.1109/asic.1992.270312

Google Scholar

[5] M.P. -H. Lin, C, -C. Hsu,Y. -T. Chang, Recnt research in clock power saving with multi-bit flip-flops, in Proceedings of IEEE International Midwest Symposium on Circuit and System(MWCAS), 2011, pp.1-4.

DOI: 10.1109/mwscas.2011.6026538

Google Scholar

[6] I.H.R. Jiang, C. L Chang, Y. M/Yang, E.Y.W. Tsai, and L.S.F. Chen, INTEGRA: Fast multibit flip-flop clustering for clock power saving,. IEEE Transactions on CAD of Intergrated Circuits and Systems , Vol. 30 , No. 12, p.1870—1882, December, (2011).

DOI: 10.1109/tcad.2011.2177459

Google Scholar