A Test Method and Test Codes Generator for Improved HT Fault Model Based on NoC

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Abstract:

NoC is a expand for SoC.The architecture of NoC is huge and complex,it leads to the crosstalk fault between internal transmission of NoC increasingly serious. Crosstalk serious impact on the signal integrity of on-chip system.A new test codes generator was designed by PSpice simulation software based on improved HT model. The generator was composed of a 16-bit counter and a 16-bit data selector.The generator was tested by PSpice software,the result showed that it satisfied the test requirements and had the advantage of portable. A crossstalk test method was proposed in this paper,we used this method on a test circuit,the result showed that the method could reduce the number of tests and save resource effectively.

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327-333

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January 2015

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© 2015 Trans Tech Publications Ltd. All Rights Reserved

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[1] S.I. Association. International Technology Roadn1apforSemieonduetors. World Semiconductor Council(1999).

Google Scholar

[2] Yuan L, He Y, Huang J, et al. A new neural-network-based fault diagnosis approach for analog circuits by using kurtosis and entropy as a preprocessor[J]. Instrumentation and Measurement, IEEE Transactions on, 2010, 59(3): 586-595.

DOI: 10.1109/tim.2009.2025068

Google Scholar

[3] He Y, Tan Y, Sun Y. Wavelet neural network approach for fault diagnosis of analogue circuits[J]. IEE Proceedings-Circuits, Devices and Systems, 2004, 151(4): 379-384.

DOI: 10.1049/ip-cds:20040495

Google Scholar

[4] Tan Y, He Y, Cui C, et al. A novel method for analog fault diagnosis based on neural networks and genetic algorithms[J]. Instrumentation and Measurement, IEEE Transactions on, 2008, 57(11): 2631-2639.

DOI: 10.1109/tim.2008.925009

Google Scholar

[5] Yiming Ouyang : Research on Key Issues for Testing Network on Chip in Chinese . HeFei University of Technology (2013).

Google Scholar

[6] Wenbiao Zhou: Research on Some Key Techniques in Mesh NoC Platform. Harbin Institute of Technology in Chinese (2008).

Google Scholar

[7] Cuviell: Fault modeling and simulation for crosstalk in system-on-chip interconnects [C]. IEEE/ACM Intemational Conference On Computer-Aided Design.Washington DC:IEEE Computer Society, l 999:297-303.

Google Scholar

[8] JQ Chen: line identification of nonlinear systems using fuzzy mode[J].Journal of Acta Automatica Sinica, Forum Vol. 24 (1998), pp.90-93.

Google Scholar

[9] Jinlin Zhang: A New Fault Model for Testing Signal Integrity in SoCs in Chinese. Journal of University of Electronic Science and Technology of China. Forum Vol. 36 (2007), pp.611-613.

Google Scholar

[10] Shuyan Jiang: Improvement and verification of interconnection crosstalk fault model of network-on-chip in Chinese. ELECTRONICM EASUREM ENT TECHNOLOGY. Forum Vol. 35 (2012), pp.123-127.

Google Scholar

[11] Ji Yang: Interconnect crosstalk test methods research on NoC in Chinese. University of Electronic Science and Technology of China. (2011).

Google Scholar

[12] Tianrui Duan: PSpice Simulation Analysis and Application for Crosstalk on Flexible Printed Circuit Board in Chinese. EMG SIMULATION (2009).

Google Scholar