The Design and Implementation of 2D-DCT Algorithm Based on FPGA

Jun Yang; Qing Han; Hong Ye Li

doi:10.4028/www.scientific.net/AMM.738-739.409

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 738-739The Design and Implementation of 2D-DCT Algorithm...

The Design and Implementation of 2D-DCT Algorithm Based on FPGA

Abstract:

DCT is the most popular image and video coding algorithm, and is widely used. Though the design of common one-dimension DCT only consists of many adders, there are a lot of limitations in the speed of processing data and the possession of system resources. This paper introduces a kind of 8 * 8 two-dimensional DCT optimization design, and implements it in FPGA. By adopting pipeline design, multipliers and adders, we reduce the resources’ possession of FPGA and improve the operational speed. At last we use the simulation by Quartus II and the performance analysis to prove the correctness and effectiveness of the design [1].

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Periodical:

Applied Mechanics and Materials (Volumes 738-739)

Pages:

409-412

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.738-739.409

Citation:

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Online since:

March 2015

Authors:

Jun Yang*, Qing Han, Hong Ye Li

Keywords:

Adder, Multiplier, Pipeline, Two-Dimensional DCT

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* - Corresponding Author

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