A Built-In Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs

Masaki Hashizume; Shohei Suenaga; Hiroyuki Yotsuyanagi

doi:10.4028/www.scientific.net/AMM.761.202

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vol. 761A Built-In Test Circuit for Detecting Open Defects...

A Built-In Test Circuit for Detecting Open Defects by IDDT Appearance Time in CMOS ICs

Abstract:

A built-in test circuit is proposed to detect an open defect in a CMOS IC by means of appearance time of dynamic supply current of the IC. A layout of an IC embedding the test circuit is designed. It is shown by Spice simulation that an open defect in the IC can be detected with the test circuit.

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Periodical:

Applied Mechanics and Materials (Volume 761)

Pages:

202-207

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.761.202

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Online since:

May 2015

Authors:

Masaki Hashizume*, Shohei Suenaga, Hiroyuki Yotsuyanagi

Keywords:

BIST, CMOS IC, IDDT Test, Open Defect

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* - Corresponding Author

References

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