A Sub-1V 0.18um Output-Capacitor-Free Digitally Controlled LDO

Wei Bin Yang; Shao Jyun Xie; Han Hsien Wang

doi:10.4028/www.scientific.net/AMM.764-765.471

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HomeApplied Mechanics and MaterialsApplied Mechanics and Materials Vols. 764-765A Sub-1V 0.18um Output-Capacitor-Free Digitally...

A Sub-1V 0.18um Output-Capacitor-Free Digitally Controlled LDO

Abstract:

The new digital control loop of the low-dropout regulator (LDO) is presented. It is composed of coarse tracking circuit and fine tracking circuit, and no external output capacitor is required to stabilize the control loop. The proposed method makes the quiescent current lower than conventional analog LDOs. The operational amplifier of the conventional LDO fails to operate at 0.7V, and the developed digital LDO in 0.18um CMOS achieved the 0.7V input voltage and 0.5V output voltage with 99.99% current efficiency and 2.6-μA quiescent current at 20mA load current. Therefore, the proposed DLDO is suitable for low power applications.

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Periodical:

Applied Mechanics and Materials (Volumes 764-765)

Pages:

471-475

DOI:

https://doi.org/10.4028/www.scientific.net/AMM.764-765.471

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Online since:

May 2015

Authors:

Wei Bin Yang*, Shao Jyun Xie, Han Hsien Wang

Keywords:

Digitally Controlled, Low Power, Low-Dropout Regulator, Output-Capacitor-Free

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* - Corresponding Author

References

[1] Y. -S. Hwang, M. -S. Lin, B. -H. Hwang and J. -J. Chen: 2008. A 0. 35μm CMOS sub-1V low-quiescent-current low-dropout regulator. Asian Solid-State Circuits Conf, p.153–156.

DOI: 10.1109/asscc.2008.4708751

Google Scholar

[2] J. -J. Chen, M. -S. Lin, H. -C. Lin and Y. -S. Hwang: 2008. Sub-1V capacitor-free low-power-consumption LDO with digital controlled loop. Asia Pacific Conf. on Circuits and Systems, p.526–529.

DOI: 10.1109/apccas.2008.4746076

Google Scholar

[3] Jackum, T. Maderbacher, G. Pribyl. W, and Riederer, R.: 2010. A digitally controlled linear voltage regulator in a 65nm CMOS process. Conf. on Electronics, Circuits, and Systems, p.982–985.

DOI: 10.1109/icecs.2010.5724678

Google Scholar

[4] Y. Okuma, K. Ishida, Y. Ryu, X. Zhang, P. Chen, K. Watanabe, M. Takamiya and T. Sakurai: 2011. 0. 5-V input digital low-dropout regulator (LDO) with 98. 7% current efficiency in 65 nm CMOS. IEICE Transactions, pp.938-944.

DOI: 10.1587/transele.e94.c.938

Google Scholar

[5] Y. -C. Chu, L. -R Chang-Chien and D. Czarkowski: 2011. Novel digitally controlled low-drop-out voltage regulator. IEICE Electron. Express, Vol. 8, No. 15: pp.1252-1259.

DOI: 10.1587/elex.8.1252

Google Scholar

[6] S. S. Chong and P. K. Chan: 2011 "A Quiescent Power-Aware Low-Voltage Output Capacitorless Low Dropout Regulator for SoC Applications. IEEE International Symposium on Circuits and Systems (ISCAS), pp.37-40.

DOI: 10.1109/iscas.2011.5937495

Google Scholar