Verification of Faulty Mechanism for Fan-Out Wafer Level Package Using Numerical Analysis

Abstract:

The manufactures of the ultra-thin and smaller semiconductor chip are required over the portable electric devices. The investigation of Fan-out wafer level package (FOWLP) is used widely, among the performance improvement and miniaturization technologies. In this paper, we obtained lots of crack near the passivation (PSV) and redistributed layer (RDL) region of FOWLP during the reliability evaluation of thermal cycling test (TCT). The generated stress and deformational behavior was observed through 2D finite-element analysis. The concentrated stress and deformational behavior are observed around the Solder ball edge and RDL & PSV edges. The crack was observed experimentally as well. The verification of the mechanism for crack generation and the validity of the finite-element analysis were verified by the structural analysis.

• Periodical: Applied Mechanics and Materials (Volumes 789-790)
• Pages: 609-612
• DOI: https://doi.org/10.4028/www.scientific.net/AMM.789-790.609
• Online since: September 2015
• Authors: Hyung Seok Yoon, Insu Jeon
• Keywords: Fan-Out Wafer Level Package (FOWLP), Finite Element Method, Thermal Cycling Test (TCT), Thermal Stress

References

[1] Fan XJ, Han Q: Design and reliability in wafer level packaging, Proc of IEEE 10th electronics packaging technology conference (2008), p.834–41.

DOI: 10.1109/eptc.2008.4763535

[2] Rahim MSK, Zhou T, Fan XJ, Rupp G: Board level temperature cycling study of large array wafer level packages, Proc of electronic components and technology conference (2009), p.898–902.

DOI: 10.1109/ectc.2009.5074119

[3] Rzepka S, Hofer E, Simon J, Meusel E, Reichl H: Stress analysis and design optimization of a wafer-level CSP by FEM simulations and experiments, IEEE Trans Electron Packag Manuf (2002), 25(2). p.127–37.

DOI: 10.1109/tepm.2002.1021638

[4] Varia B, Fan XJ, Han Q: Effects of design, structure and material on thermal–mechanical reliability of large array wafer level packages, ICEPT-HDP (2009).

DOI: 10.1109/icept.2009.5270586

[5] Kim D-H, Elenius P, Johnson M, Barrett S: Solder joint reliability of a polymer reinforced wafer level package, Microelectron Reliab (2002), 42. p.1837.

DOI: 10.1016/s0026-2714(02)00102-6

[6] Liu P, Wang Z, Chiang D, Renavikar M, Pathangey B, Tanikella R, et al: Electromigration failure mechanisms in P1264 SnPb and P1266 SnAg solder joints, Intel Assembly Test Technol J (2006), 9. p.473–82.

[7] Reche JHJ, Kim DH: Wafer level packaging having bump-on-polymer structure Microelectron Reliab (2003), 43. p.879–94.

DOI: 10.1016/s0026-2714(03)00058-1

[8] E. Kuah, JY. Hao: Encapsulation Challenges for Wafer Level Packaging, Microelectronics and Packaging Conference (2009).

[9] S. C. Chong, C. H. Khong: Process Challenges and Development of eWLP, Electronics Packaging Technology Conference 12. (2010), pp.527-531.