Applied Mechanics and Materials Vol. 926

Abstract: Multipath interference poses a significant challenge in satellite-based navigation systems, including NAVIC (Navigation with Indian Constellation), degrading the accuracy of position estimates. This study proposes a comprehensive approach to address multipath errors in NavIC receivers, combining multipath error calculation using the code minus carrier method with multipath reduction through mode decomposition techniques EMD- empirical mode decomposition, VMD-variational mode decomposition, and SVMD-successive variational mode decomposition. Data was collected from a NavIC receiver located at KLEF University in Guntur, India with latitude 16.44 N, and longitude 80.62 E during the period from April 12th to 14th, 2017. Initially, multipath errors are calculated by subtracting NavIC carrier phase measurements from code phase measurements, providing insights into the magnitude of multipath interference. Subsequently, the received signal is decomposed using EMD, VMD, and SVMD to extract intrinsic modes or oscillatory components representing different signal characteristics. The direct signal is reconstructed by selectively filtering or removing multipath-related modes, reducing multipath interference. To evaluate the effectiveness of each decomposition method, the SDE (standard deviation error) of the reconstructed multipath signal is computed. The decomposition method yielding the lowest SDE is identified as the optimal approach for multipath reduction in NavIC receivers. By integrating the code minus carrier method with mode decomposition techniques, significant enhancements in navigation performance can be achieved, facilitating reliable and precise positioning for various applications.

Abstract: Objective: Designing an effective multiplier assists in enhancing microprocessor system performance and complex digital signal processing. The main objective of this work is to design a 16 × 16 Wallace structure multiplier with a parallel prefix adder and evaluate the design's area, power performance, and utilization of resources using three distinct architectures: pipeline, wave pipeline, and hybrid pipeline. Methods: The 16 × 16 Wallace tree multiplier is designed using a parallel prefix adder in the Verilog HDL environment. The Wallace tree multiplier is integrated with a 3-tap FIR filter, and performances are evaluated through a distinct architecture by applying an ECG signal. It is suggested to use a hybrid wave-pipeline multiplier architecture to increase the Wallace tree multiplier's speed and reduce the delay. Delay optimization: In a hybrid pipelining system, the clock duration is relative to the maximum performance difference, whereas in a standard pipeline method, it is comparative to the greatest delay. In the hybrid pipeline multiplier, the last two rows of the partial products are added by parallel prefix adders (PPAs). To lower the delay, the hybrid multiplier uses the Han-Carlson adder for addition. Findings: The hybrid multiplier is executed in the FIR filter for ECG denoising in order to validate its performance. Xilinx ISE is used to synthesize the multiplier structures, whereas Verilog HDL is used for design. Comparing the suggested hybrid design to traditional pipelined designs, the outcome demonstrates that performance is increased while resource use and power optimization are reduced. Novelty: In this work, the hybrid pipeline approach has been applied to the existing Wallace multiplier architecture, and it offers better results in terms of power, area, and delay. The results indicate that the proposed hybrid design outperforms compared to traditional pipelined designs, achieving 48.83% improved delayed performance along with reduced resource usage and power consumption.

Abstract: Single-event and multi-bit effects are the result of radiation and ionized particles in extreme settings like space, which can lead to random failures on any electronic component. To keep the functionality of the device unaltered, these must be reduced. FPGA plays a vital role in satellite and aerospace applications in which dynamic reconfiguration essential. Cascaded Integration Comb (CIC) filters are mostly utilized in multidata signal processing and satellite communication systems as low pass filters in rate converter modules. The configuration memory of FPGA used to design CIC filter is affected with soft errors with single and multi-bit due to high radiation in higher altitude and different environment regions. The methods like triple modular redundancy (TMR) is very effective in overcoming single event transients and single-event upsets, but incur area three times of the original module. Scrubbing is a serial process method that goes over each word in memory in search of mistakes that need to be fixed. It entails a non-negligible Time to Detect (TTD) prior to repair, in which time further functionality could happen parallely and jeopardize the system. Thus, effective multi-bit error detection correction of configuration memory in FPGA is essential in maintaining the application to work for an extended time. In this research, built-in multi-bit error correction for FPGA configuration memory is proposed. The proposed work can replace time consuming scrubbing process and high area utilizing TMR for error tolerant design. To safeguard FPGA, a multi-bit error detection and correction system is performed by using multi dimensional parity with minimum area overhead. Furthermore, the suggested method can identify and rectify error when triggered by an interrupt manager reducing time to detect (TTD).

Abstract: In the recent era- very frequently people come across health issues due to consumption of poor-quality food items- which leads to issues such as food poisoning, vomiting, diarrhea, etc., For a full development of fruits and vegetables, all the nutrients are necessary during its growth. But due to circumstances like soil defects, infections, water scarcity, waterlogging, etc., the vegetables & fruits gets infected with some diseases. So there arises a necessity of a system which inspects for any presence of disease in fruits & vegetables, with reduced manual intervention. This paper provides a detailed overview of a system developed using the Python programming language. Its aim is to recognize and classify various fruits and vegetables, while also identifying any diseases affecting them and determining the specific type of infection. In order to recognize the details accurately, the system is designed to use convolutional neural networks (CNN) and the results are displayed using computer vision techniques. The analysis, implementation, and future improvements of the proposed system are briefed in this paper. For this, we have used Anaconda navigator software (Jupyter notebook, IDLE).