Speculative High Performance Computation on Heterogeneous Multi-Core

Article Preview

Abstract:

Thread level speculation has been proposed and researched to parallelize traditional sequential applications on homogeneous multi-core architecture. In this paper, a heterogeneous multi-core hardware simulation system is present, which provides with TLS execution mechanism. With a novel TLS programming model and a number of new speculative tuning techniques, benchmark Gzip is parallelized from-3% to 195% on a four-core processor, and the speedup of the test benchmarks are 30%, 43% and 156%, respectively with arbitrary, hotspot and insight speculation.

You might also be interested in these eBooks

Info:

Periodical:

Advanced Materials Research (Volumes 1049-1050)

Pages:

2126-2130

Citation:

Online since:

October 2014

Export:

Price:

Permissions CCC:

Permissions PLS:

Сopyright:

© 2014 Trans Tech Publications Ltd. All Rights Reserved

Share:

Citation:

* - Corresponding Author

[1] L. Hammond, B.A. Hubbert, et al: The Stanford Hydra CMP , IEEE Micro(2000), 71.

Google Scholar

[2] J. Renau, J. Tuck, et al: Tasking with Out-of-Order Spawn in TLS Chip Multiprocessors: Microarchitecture and Compilation, ICS(2005).

DOI: 10.1145/1088149.1088173

Google Scholar

[3] SESC simulator, http: /sesc. sourceforge. net.

Google Scholar

[4] W. Liu, J. Tuck, et al: POSH: a TLS compiler that exploits program structure, PPoPP(2006).

Google Scholar

[5] J. W. Davidson, S. Jinturkar: Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation, Micro(1995).

DOI: 10.1109/micro.1995.476820

Google Scholar

[6] K. Olukotun, L. Hammond, J. Laudon: Chip Multiprocessor Architecture Techniques to Improve Throughput and Latency, San Francisco: M&C Publisher, (2008).

DOI: 10.1007/978-3-031-01720-9

Google Scholar

[7] C. Ding, X. Shen, et al: Software behavior oriented parallelization, PLDI(2007).

Google Scholar

[8] V. Krishnan and J. Torrellas: A Chip-Multiprocessor Architecture with Speculative Multithreading, IEEE Trans. Comput(1999), 866.

DOI: 10.1109/12.795218

Google Scholar

[9] http: /www. gzip. org.

Google Scholar

[10] J. Gilchrist: Parallel data compression with Bzip2, PDCS(2004).

Google Scholar

[11] R. Kumar, K.I. Farks, et al: Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction, MICRO(2003).

Google Scholar

[12] R. Kumar, D. M. Tullsen, et al: Single-ISA heterogeneous multi-core architectures for multithreaded workload performance, ISCA(2004).

DOI: 10.1109/isca.2004.1310764

Google Scholar

[13] Y. Luo, W. Hsu: The Design and Implementation of Heterogeneous Multicore Systems for Energy-efficient Speculative Thread Execution, ACM Trans. on Architecture and Code Optimization(2013).

DOI: 10.1145/2541228.2541233

Google Scholar