[1]
Eric Sun, James Kim, John Liu. A 400Ms/s, 8-b Folding and Current interpolating ADC in 0. 25 μm CMOS.
Google Scholar
[2]
Marcel J.M. Pelgrom. Analog-to-Digital Conversion. The Netherlands: NXP Semiconductor, 2010, 175-176.
Google Scholar
[3]
B. Yu, et al. A 900Ms/s 6b Interleaved CMOS Flash ADC. Proceedings of the Custom Integrated Circuits Conference, 2001: 149-152.
DOI: 10.1109/cicc.2001.929744
Google Scholar
[4]
Michael P. Flynn, Ben Sheahan. A 400-Msample/s, 6-b CMOS Folding and Interpolating ADC. IEEE Journal of Solid-State Circuit. VOL. 33, NO. 12, Decembei 1998: 1932-(1938).
DOI: 10.1109/4.735533
Google Scholar
[5]
Ali A M, Morgan A, Dillon C, et al. A 16 b 250MS/s IF-sampling pipelined A/D converter with background calibration. IEEE International Solid-State Circuit Conference Digest of Technical Papers, 2010: 292-293.
DOI: 10.1109/isscc.2010.5433923
Google Scholar
[6]
Robert C. Taft, Pier Andrea, Maria Rosaria Tursi, et al. A 1. 8 V 1. 0GS/s 10b Self-Calibrating Unified-Folding-Interpolating ADC With 9. 1 ENOB at Nyquist Frequency. IEEE JOURNAL OF SOLID-STATE CIRCUIT. VOL. 44, NO. 12, DECEMBER 2009: 3294-3304.
DOI: 10.1109/jssc.2009.2032634
Google Scholar
[7]
Yu Jinshan, Zhang Ruitao, Zhang Zhengping, et al. A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0. 18-μm CMOS technology. Journal of Semiconductors, Vol. 32, No. 1, January 2011. pp.108-115.
DOI: 10.1088/1674-4926/32/1/015006
Google Scholar