A Digital Calibration Method and Circuit for ADCs with a Fold-Interpolation and Pipeline Structure

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Abstract:

A structure of ADCs which combines fold-interpolation and pipeline is introduced, as well as corresponding digital calibration method. The simulation shows that the performances of the ADC after calibration are improved a lot. The SFDR achieves 62dB at a sampling rate of 800MHz, when the input analog signal is at 397MHz.

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Advanced Materials Research (Volumes 1049-1050)

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699-702

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October 2014

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© 2014 Trans Tech Publications Ltd. All Rights Reserved

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