The Intelligent Dispenser Control System Design Based on FPGA and SRAM

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Abstract:

he proposed FPGA and SRAM peristaltic intelligent dispensing machine control system design based on the can not only quickly, accurate, intelligent control of dispensing glue, to achieve precise control of the liquid flow rate, can also be used for other work in the intermittent condition of instrument. In addition, through the use of single-chip microcomputer to control the step motor, to achieve the control purpose of peristaltic pump. The user input the motor rotation speed and rotation direction of rotation of the step number, at the same time flexibly, can obtain from the MCU according to its input data generated by a series of control signal, the motor rotate normally. In the dispensing process, through the external interrupt, can be changed at any time of peristaltic pump working mode. This system realizes the machine position control, speed control, interpolation calculation of real-time task, and construct the concept of digital dispenser system. Practice has proved that this system overcomes the dispensing accuracy of traditional time pressure dispensing machine is not high, prone to smearing and other shortcomings, improve the speed and accuracy of the dispensing.

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Periodical:

Advanced Materials Research (Volumes 1079-1080)

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1026-1029

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Online since:

December 2014

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© 2015 Trans Tech Publications Ltd. All Rights Reserved

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[1] Chen XB Schoenau G, Zhang W J Modeling of Tine-pressure Fluid Dispensing Process[J], IEEE Transactions on Electronics Packaging Manufacturing 2012, 23 (4): 300-305.

DOI: 10.1109/6104.895075

Google Scholar

[2] Remy Lin, Craig Lazinsky. Dispensing for High yield assembly[J/OL]. Electronics Engineer_Setember_2012. http: /www. eetasia. com/ARTICLES/2013SEP01_DH_MAT_SMT_TA. PDF.

Google Scholar

[3] ZHAO J,WANG Y L, LIU M F, et al. Research on the test of SRAM-based FPGA[J]. Semiconductor technology. 2012. 32(9): 804-808.

Google Scholar

[4] LIU Y, MEI D CH,YU ZH ZH. Design of QDR SRAM controller and realization of FPGA[J]. Modern electronic technique, 2012, 30(2): II-16.

Google Scholar

[5] WANG CH,GAO M G, XIE M,et al. New arbitrary waveform generator based on flash and FPGA[J]. Chinese Journal of Scientific Instrument, 2011, 27(6); 2356-2357.

Google Scholar

[6] DU G, SUN CH,CHEN AN J. Design of sixteen bits digital frequency divider on FPGA[J]. Chinese Journal of Scientific Instrument, 2011, 27(6): 875-876.

Google Scholar