[1]
Qin, L., Kong, L., Zhu, Y., Zhang, H., Lyu, Y., & Wang, L. (2024). Short-channel effect suppression and footprint reduction in double gate-all-around field effect transistors and inverters based on two-dimensional materials. ACS Applied Electronic Materials, 6(3), 2029–2038.
DOI: 10.1021/acsaelm.4c01319
Google Scholar
[2]
Joshi, G., & Choudhary, A. (2011). Analysis of short channel effects in nanoscale MOSFETs. International Journal of Nanoscience, 10(1 & 2), 275-278.
DOI: 10.1142/s0219581x11007910
Google Scholar
[3]
Liu, A.-C., Tu, P.-T., Langpoklakpam, C., Huang, Y.-W., Chang, Y.-T., Tzou, A.-J., Hsu, L.-H., Lin, C.-H., Kuo, H.-C., & Chang, E. Y. (2021). The evolution of manufacturing technology for GaN electronic devices. Micromachines, 12(7), 737.
DOI: 10.3390/mi12070737
Google Scholar
[4]
del Alamo, J. A. (2011). Nanometre-scale electronics with III-V compound semiconductors. Nature, 479(7373), 317–323.
DOI: 10.1038/nature10677
Google Scholar
[5]
Das, M., Sen, D., Sakib, N. U., Ravichandran, H., Sun, Y., Zhang, Z., Ghosh, S., Venkatram, P., Subbulakshmi Radhakrishnan, S., Sredenschek, A., Yu, Z., Sarkar, K. J., Sadaf, M. U. K., Meganathan, K., Pannone, A., Han, Y., Sanchez, D. E., Somvanshi, D., Sofer, Z., & Terrones, M. (2024). High-performance p-type field-effect transistors using substitutional doping and thickness control of two-dimensional materials. Nature Electronics, 8(1), 24–35.
DOI: 10.1038/s41928-024-01265-2
Google Scholar
[6]
Li, Y. (2023). Two-dimensional field effect transistor [Master's thesis, Washington University in St. Louis]. McKelvey School of Engineering Theses & Dissertations.
Google Scholar
[7]
Huang, X., Liu, C., & Zhou, P. (2022). 2D semiconductors for specific electronic applications: From device to system. npj 2D Materials and Applications, 6(1).
DOI: 10.1038/s41699-022-00327-3
Google Scholar
[8]
Duan,H. (2024). From MOSFET to FinFET to GAAFET: The evolution, challenges, and future prospects. Applied Computational Engineering, 50, 113,50,113-120.
DOI: 10.54254/2755-2721/50/20241285
Google Scholar
[9]
Raj, P., Chang-Liao, K., & Tiwari, P. K. (2024). Electrical characteristics of Si0.7Ge0.3/Si heterostructure-based n-type GAA MOSFETs. Microelectronic Engineering, 292, 112226.
DOI: 10.1016/j.mee.2024.112226
Google Scholar
[10]
Rajawat, V. S., Choudhary, B., & Kumar, A. (2024). Performance Assessment of High-k SOI GaN FinFET with Different Fin Aspect Ratio for RF/Wireless Applications. Wireless Personal Communications, 136(2), 867–882.
DOI: 10.1007/s11277-024-11293-y
Google Scholar
[11]
Song, Y., Bhattacharyya, A., Karim, A., Shoemaker, D., Huang, H., Roy, S., McGray, C., Leach, J. H., Hwang, J., Krishnamoorthy, S., & Choi, S. (2023). Ultra-Wide Band GAP GA2O3-on-SIC MOSFETs. ACS Applied Materials & Interfaces, 15(5), 7137–7147.
DOI: 10.1021/acsami.2c21048
Google Scholar
[12]
Liao, F., Guo, Z., Wang, Y., Xie, Y., Zhang, S., Sheng, Y., Tang, H., Xu, Z., Riaud, A., Zhou, P., Wan, J., Fuhrer, M. S., Jiang, X., Zhang, D. W., Chai, Y., & Bao, W. (2019). High-Performance logic and memory devices based on a Dual-Gated MOS2 architecture. ACS Applied Electronic Materials, 2(1), 111–119.
DOI: 10.1021/acsaelm.9b00628
Google Scholar
[13]
Hong, J. H., Kang, M. S., Ha, I., Park, H.-L., Park, K., Jeon, J., Yoo, W., Kim, J., Chung, C., Park, S. M., & Cho, S. B. (2025). Residual strain optimization in 3D MOSFET structures for enhanced mobility via nanoscale heat transfer. Journal of Applied Physics, 137(1)
DOI: 10.1063/5.0234072
Google Scholar
[14]
Chaudhry, A., & Kumar, M. J. (2004). Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: A review. IEEE Transactions on Device and Materials Reliability, 4(1), 99–109.
DOI: 10.1109/tdmr.2004.824359
Google Scholar
[15]
Takagi, S., Tezuka, T., Irisawa, T., Nakaharai, S., Maeda, T., Numata, T., Ikeda, K., & Sugiyama, N. (2006). Hole mobility enhancement of p-MOSFETs using global and local Ge-channel technologies. Materials Science and Engineering B, 135(3), 250–255.
DOI: 10.1016/j.mseb.2006.08.015
Google Scholar
[16]
Li, P., Liao, W., Shih, C., Kuo, T., Lai, L., Tseng, Y., & Tsai, M. (2003). High performance Si/SiGe heterostructure MOSFETs for low power analog circuit applications. Solid-State Electronics, 47(6), 1095–1098.
DOI: 10.1016/s0038-1101(02)00465-3
Google Scholar
[17]
Srivastava, M. (2025, February 28). Power MOSFET Market Analysis by type, power rate, application and region through 2025 to 2035. https://www.futuremarketinsights.com/reports/power-mosfet-market.
Google Scholar
[18]
Liao, M., Sun, H., & Koizumi, S. (2024). High-temperature and high-electron mobility metal-oxide-semiconductor field-effect transistors based on n-type diamond. Advanced Science, 11(6), 2306013
DOI: 10.1002/advs.202306013
Google Scholar
[19]
Li, Y., & Zhang, X. (2023). Reliability of buried InGaAs channel n-MOSFETs with an InP barrier layer under PBTI stress. Frontiers in Physics, 8, 51
DOI: 10.3389/fphy.2020.00051
Google Scholar
[20]
Adhikari, M. S., & Singh, Y. (2015). High-performance dual-channel InGaAs MOSFET for small signal RF applications. Electronics Letters, 51(15), 1203–1205.
DOI: 10.1049/el.2015.0980
Google Scholar
[21]
Technology III-V MOSFETs. (2008). In Compound Semiconductor. https://engineering.purdue.edu/~yep/Papers/CSApr08Ye.pdf
Google Scholar
[22]
Mo, J., Chen, H., Wang, Z., & Yu, F. (2017). High frequency InGaAs MOSFET with nitride sidewall design for low power application. Journal of Sensors, 2017, 1–9.
DOI: 10.1155/2017/4078240
Google Scholar
[23]
Arns, R. G. (1998). The other transistor: Early history of the metal-oxide semiconductor field-effect transistor. IEEE Engineering Science and Education Journal, 7(5), 233–240.
DOI: 10.1049/esej:19980509
Google Scholar
[24]
Rim, K., Welser, J., Hoyt, J. L., & Gibbons, J. F. (1995, December). Enhanced hole mobilities in surface-channel strained-Si p-MOSFETs. In International Electron Devices Meeting 1995 (pp.517-520). IEEE.
DOI: 10.1109/iedm.1995.499251
Google Scholar
[25]
Wilk, G. D., Wallace, R. M., & Anthony, J. M. (2001). High-κ gate dielectrics: Current status and materials properties considerations. Journal of Applied Physics, 89(10), 5243–5275.
DOI: 10.1063/1.1361065
Google Scholar
[26]
Bohr, M., Chau, R., Ghani, T., & Mistry, K. (2007). The High-K solution. IEEE Spectrum, 44(10), 29–35.
DOI: 10.1109/mspec.2007.4337663
Google Scholar
[27]
Hu, N. C., Bokor, J., King, N. T., Anderson, E., Kuo, C., Asano, K., Takeuchi, H., Kedzierski, J., Lee, N. W., & Hisamoto, D. (2000). FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Transactions on Electron Devices, 47(12), 2320–2325.
DOI: 10.1109/16.887014
Google Scholar
[28]
Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, V., & Kis, A. (2011). Single-layer MoS₂ transistors. Nature Nanotechnology, 6, 147–150.
DOI: 10.1038/nnano.2010.279
Google Scholar
[29]
Desai, S. B., Madhvapathy, S. R., Sachid, A. B., Llinas, J. P., Wang, Q., Ahn, G. H., Pitner, G., Kim, M. J., Bokor, J., Hu, C., Wong, H. P., & Javey, A. (2016). MoS₂ transistors with 1-nanometer gate lengths. Science, 354(6308), 99–102.
DOI: 10.1126/science.aah4698
Google Scholar
[30]
Franklin, A. D. (2015). Nanomaterials in transistors: From high-performance to thin-film applications. Science, 349(6249).
DOI: 10.1126/science.aab2750
Google Scholar
[31]
Yao, J., & Yang, G. (2020). All-2D architectures toward advanced electronic and optoelectronic devices. Nano Today, 36, 101026.
DOI: 10.1016/j.nantod.2020.101026
Google Scholar
[32]
Scappucci, G., Taylor, P. J., Williams, J. R., Ginley, T., & Law, S. (2021). Crystalline materials for quantum computing: Semiconductor heterostructures and topological insulators exemplars. MRS Bulletin, 46(7), 596–606.
DOI: 10.1557/s43577-021-00147-8
Google Scholar
[33]
Singer, P. (2020, March 13). A 300mm Platform for 2D-Material Based MOSFET Devices - Semiconductor Digest. Semiconductor Digest.
Google Scholar
[34]
Wei, T., Han, Z., Zhong, X., Xiao, Q., Liu, T., & Xiang, D. (2022). Two dimensional semiconducting materials for ultimately scaled transistors. iScience, 25(10), 105160.
DOI: 10.1016/j.isci.2022.105160
Google Scholar
[35]
Introducing 2D materials in the logic technology roadmap | imec. (n.d.). Www.imec-Int.com. https://www.imec-int.com/en/articles/introducing-2d-materials-logic-technology-roadmap-five-good-reasons-three-major-challenges.
Google Scholar
[36]
Knobloch, T., Selberherr, S., & Grasser, T. (2022). Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials. Nanomaterials, 12(20), 3548.
DOI: 10.3390/nano12203548
Google Scholar
[37]
Zhang, L., et al. (2024). The roadmap of 2D materials and devices toward chips. Nano-Micro Letters, 16, 119
DOI: 10.1007/s40820-023-01273-5
Google Scholar
[38]
Schram, T., Sutar, S., Radu, I., & Asselberghs, I. (2022). Challenges of wafer-scale integration of 2D semiconductors for high-performance transistor circuits. Advanced Materials, 34, 2109796.
DOI: 10.1002/adma.202109796
Google Scholar
[39]
Lin, Y., McGuire, F., Noyce, S., Williams, N., Cheng, Z., Andrews, J., & Franklin, A. D. (2019). Effects of gate stack composition and thickness in 2-D negative capacitance FETs. IEEE Journal of the Electron Devices Society, 7, 645–649.
DOI: 10.1109/jeds.2019.2922441
Google Scholar
[40]
Kang, T., Park, J., Jung, H., Choi, H., Lee, S.-M., Lee, N., Lee, R.-G., Kim, G., Kim, S.-H., Kim, H., Yang, C.-W., Jeon, J., Kim, Y.-H., & Lee, S. (2024). High-κ dielectric (HfO₂)/2D semiconductor (HfSe₂) gate stack for low-power steep-switching computing devices. Advanced Materials, 36, 2312747.
DOI: 10.1002/adma.202312747
Google Scholar
[41]
Kamaei, S., Saeidi, A., Gastaldi, C., et al. (2021). Gate energy efficiency and negative capacitance in ferroelectric 2D/2D TFET from cryogenic to high temperatures. npj 2D Materials and Applications, 5, 76.
DOI: 10.1038/s41699-021-00257-6
Google Scholar
[42]
Uniyal, M., Bhatt, S., Ghildiyal, A., Saxena, R., Kashyap, S., Joshi, A., Kukreti, C., & Ghoshal, S. K. (2024). Dielectric properties of sodium potassium tantalate (NA0.5 K0.5 TAO3). Ceramics International
DOI: 10.1016/j.ceramint.2024.09.093
Google Scholar
[43]
Qian, Q., Lei, J., Wei, J., Zhang, Z., Tang, G., Zhong, K., Zheng, Z., & Chen, K. J. (2019). 2D materials as semiconducting gate for field-effect transistors with inherent over-voltage protection and boosted ON-current. npj 2D Materials and Applications, 3(1).
DOI: 10.1038/s41699-019-0106-6
Google Scholar
[44]
Meena, S., Sharma, N., & Jogi, J. (2023). Sub-5 nm 2D semiconductor-based monolayer field-effect transistor: Status and prospects. Physica Status Solidi (A), 220(11).
DOI: 10.1002/pssa.202200526
Google Scholar
[45]
Wu, Y. (2023). Evolution, Challenges and Applications of Modern MOSFETs. Applied Computational Engineering, 24(1), 294–301.
Google Scholar
[46]
Saxena, R., Kotnala, S., Bhatt, S., Uniyal, M., Rawat, B., Negi, P., & Riyal, M. K. (2025). A Review on Green Synthesis of Nanoparticles Toward Sustainable Environment. Sustainable Chemistry for Climate Action, 100071.
DOI: 10.1016/j.scca.2025.100071
Google Scholar
[47]
Kumar, A., & Chaturvedi, S. (2025). Negative capacitance double-gate MOSFET for advanced low-power electronic applications. Microelectronics Journal, 159, 106656.
DOI: 10.1016/j.mejo.2025.106656
Google Scholar
[48]
Negi, P., Rawat, B., Joshi, N. C., Ahmad, W., Kumar, N., Upadhyay, S., Parmar, K. P. S., Saxena, R., Dhyani, R. D., Khati, P. S., & Rana, A. (2024). Hydrothermal Synthesis of Nitrogen-doped CQDs of Rubus Niveus Leaves for Fluorescent pH Sensing and Photocatalytic Applications. Malaysian Journal of Science, 43(3), 13–21.
DOI: 10.22452/mjs.vol43no3.2
Google Scholar