Leakage Reduction of Improved CAL Registers Using MTCMOS Power-Gating Scheme in Nanometer CMOS Processes
With rapid technology scaling, the leakage dissipation that begins to replace dynamitic dissipation is becoming a major source in CMOS circuits because of the increasing sub-threshold leakage current in nanometer CMOS processes. This paper introduces a MTCMOS power-gating technique, which is used for an adiabatic register file based on improved CAL (Clocked Adiabatic Logic) to reduce leakage dissipation in sleep mode. A 32 X 32 single-phase adiabatic register file are verified using HSPICE in different processes, threshold voltage, and active ratios, and BSIM4 model is adopted to reflect the leakage currents. Simulation results show that leakage losses are greatly reduced.
Donald C. Wunsch II, Honghua Tan, Dehuai Zeng, Qi Luo
J. G. Zhu and J. P. Hu, "Leakage Reduction of Improved CAL Registers Using MTCMOS Power-Gating Scheme in Nanometer CMOS Processes", Advanced Materials Research, Vols. 121-122, pp. 281-286, 2010