Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction

Jian Ping Hu; Yu Zhang

doi:10.4028/www.scientific.net/AMR.159.180

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 159Gate-Length Biasing Technique of Complementary...

Gate-Length Biasing Technique of Complementary Pass-Transistor Adiabatic Logic for Leakage Reduction

Abstract:

Scaling down sizes of MOS transistors has resulted in dramatic increase of leakage currents. To decrease leakage power dissipations is becoming more and more important in low-power nanometer circuits. This paper proposes a gate-length biasing technique for complementary pass-transistor adiabatic logic (CPAL) circuits to reduce sub-threshold leakage dissipations. The flip-flops based on CPAL circuits with gate-length biasing techniques are presented. A traffic light controller using two-phase CPAL with gate-length biasing technique is demonstrated at 45nm CMOS process. The BSIM4 model is adopted to reflect the characteristics of the leakage currents. All circuits are simulated using HSPICE. Simulation results show that the CPAL traffic light controller with the gate-length biasing technique attains 20% to 5% energy savings compared with the one using the original gate length 25MHz to 200MHz.

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Periodical:

Advanced Materials Research (Volume 159)

Pages:

180-185

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.159.180

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Online since:

December 2010

Authors:

Jian Ping Hu, Yu Zhang

Keywords:

Complementary Pass-Transistor Adiabatic Logic, Gate-Length Biasing, Leakage Reduction, Nanometer Circuits

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