Exploring IEEE 1149.1 EXTEST for External Interconnect of a Multi-FPGA System

Abstract:

An approach for detecting open and short faults on the interconnect wires of a multi-FPGA system will be presented in this paper. In a multi-FPGA system with N interconnects, this approach can detect whether and where an open fault occurs by executing the IEEE 1149.1 JTAG EXTEST instruction once. To detect a single short fault, on the other hand, needs execution of times where . If multiple short connections exist, this approach will only detect the first short fault. The test time is thus greatly reduced for finding a single short fault per chip. Simulation results demonstrate that this approach can be easily implemented and determines accurate locations of the open/short faults.

• Periodical: Advanced Materials Research (Volume 159)
• Pages: 538-543
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.159.538
• Online since: December 2010
• Authors: Yan Zhao, Xiao Wei Han, Li Hua Wu, Fang Yu
• Keywords: External Interconnect, EXTEST, IEEE 1149.1, Multi-FPGA

References

[1] IEEE Standard Test Access Port and Boundary-Scan Architecture (1993).

[2] Kuen-Jong Lee, Boundary Scan and Core-Based Testing, VLSI Test Principles and Architectures Design for Testability, pp.557-572 (2006).

DOI: 10.1016/b978-012370597-6/50014-7

[3] S. Hauch, G. Borriello, and C. Ebeling, IEEE Tran. Very Large Scale Integration (VLSI) Systems, Vol. 6 No. 3, pp.400-408 (1998).

DOI: 10.1109/92.711311

[4] M. Buttes, J. Batcheller, and J. Varghese, Proc. 1992 IEEE Int'1 Conf. Computer Design: VLSI in Computers and Processors, pp.138-141 (1992).

[5] M.A.S. Khalid and J. Rose, ACM/SIGDA Int'1 Symp. Field Programmable Gate Arrays, pp.45-54 (1998).