Exploring IEEE 1149.1 EXTEST for External Interconnect of a Multi-FPGA System

Abstract:

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An approach for detecting open and short faults on the interconnect wires of a multi-FPGA system will be presented in this paper. In a multi-FPGA system with N interconnects, this approach can detect whether and where an open fault occurs by executing the IEEE 1149.1 JTAG EXTEST instruction once. To detect a single short fault, on the other hand, needs execution of times where . If multiple short connections exist, this approach will only detect the first short fault. The test time is thus greatly reduced for finding a single short fault per chip. Simulation results demonstrate that this approach can be easily implemented and determines accurate locations of the open/short faults.

Info:

Periodical:

Edited by:

Dehuai Zeng

Pages:

538-543

DOI:

10.4028/www.scientific.net/AMR.159.538

Citation:

Y. Zhao et al., "Exploring IEEE 1149.1 EXTEST for External Interconnect of a Multi-FPGA System", Advanced Materials Research, Vol. 159, pp. 538-543, 2011

Online since:

December 2010

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$35.00

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