Electronic package development is driven by the continuous increase in demands for miniaturization of products with enhanced performances. Three Dimensional System in Package (3D SiP) has become a key technology to satisfy the request. The 3D SiP with Through Silicon Via (TSV) technology is developed for chip to chip stacking in a package with superior electrical performance than conventional structures. In this study, we evaluate the thermal performance of 3D SiP with TSV technology using Finite Element Method (FEM). The evaluation topics covered impacts of various materials of mold, 3D SiP models with and without TSV, and various convention conditions. The results indicated that the role of TSVs in heat dissipation is not obvious in this study, and the maximum temperature merged in the center of the chip1 under different conditions which are considered.