With the development of integrated circuit technology, it is more and more difficult for debugging circuits. Generally, to achieve a powerful debugging capability of circuits is often at the expense of larger cost of hardware overhead .This paper propose a method of debugging structure designed in full-custom CPU based on scan-set testability methods and combed with the boundary-scan technology. This debugging structure can reduces much scan chains hardware overheads and is applicable to all general-purpose CPU chips. Moreover, it owns a powerful debugging capability which is observing and controlling the internal registers of circuits from JTAG port. This structure only increases the difficulty of the circuit logic design, but greatly decreases the cost of hardware.