A Model of Threshold Voltage in FinFET

Jian Liu; Li Li; X.H. Zhang

doi:10.4028/www.scientific.net/AMR.216.167

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 216A Model of Threshold Voltage in FinFET

A Model of Threshold Voltage in FinFET

Abstract:

A physics-based threshold voltage model is proposed, according to the electrostatics distribution in Si body of FinFET which is obtained by 2-D numerical simulation. Threshold voltage of FinFET calculated from the model is matched with results of numerical simulation. Influences of polysilicon gate doping concentration, Si body doping concentration, the width and height of Si body and the gate oxide thickness on threshold voltage were investigated. As results,Si body doping concentration, gate doping concentration and the width of Si body have been found to be the most important parameters for the design of threshold voltage of FinFET-like devices.

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Advanced Materials Research (Volume 216)

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167-170

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.216.167

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Online since:

March 2011

Authors:

Jian Liu, Li Li, X.H. Zhang

Keywords:

FinFET, Modeling, Numerical Simulation, Threshold Voltage

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References

[1] X. Huang, W. C. Lee, C. Kuo, et al. Sub-50 nm FinFET: PMOS. IEDM Tech. Dig. Dec. 1999. 67-70.

Google Scholar

[2] V. P. Trivedi and J. G. Fossum. Scaling fully depleted SOI CMOS. IEEE Trans. Electron Devices, 2003. vol 50(10): 2095-2103.

DOI: 10.1109/ted.2003.816915

Google Scholar

[3] S. Cristoloveanu and S.S. Li, Elecrical characterization of silicon-on-insulator Materials andDevices. Boston, MA: Kluwer, (1995).

Google Scholar

[4] R. Chau, B. Doyle, J . Kavalieros, et al. Advanced depleted-substrate transistors: Single-gate, double-gate, and tri-gate. Proc. Int. Conf. Solid State Devices and Materiials. Sept. 2002. 68-69.

DOI: 10.7567/ssdm.2002.d-1-1

Google Scholar

[5] B. Doyle, B. Boyanov, S. Datta, et al. Tri-gate fully depleted CMOS transistors: Fabrication, design, and layout. Proc. VLSI Tech. Symp. June 2003. 133-134.

DOI: 10.1109/vlsit.2003.1221121

Google Scholar

[6] C. Zeng and D.W. Barlage. Analytical threshold voltage model for design and evaluation of Tri-gate MOSFETS. Semiconductor Device Research Symposium, 2003 Internationa]. Dec. 2003. 232-233.

DOI: 10.1109/isdrs.2003.1272075

Google Scholar

[7] Xia Zhiliang, Liu Xiaoyan, Liu Enfeng, et al. 3D simulation of multi-gate MOSFET with sub-100nm. Chinese Journal of Semicoductors, 2003. vol 24 supplement(5): 140-143.

Google Scholar

[8] k. Suzuki, T. Tanaka, Y. Tosaka, et al. Analytical surface potential expression for thin -filmdouble-gate SOI MOSFETs. Solid-state Electornics, 1994. Vol. 37(2): 327-332.

DOI: 10.1016/0038-1101(94)90085-x

Google Scholar