[1]
Dancy, R. Amirtharajah, A. Chandrakasan, Highefficiency multiple-output DC–DC conversion for lowvoltage systems, IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (2000).
DOI: 10.1109/92.845892
Google Scholar
[2]
Peterchev, J. Xiao, S. Sanders, Architecture and IC implementation of a digital VRM controller, IEEE Transactions on Power Electronics 18 (2006).
DOI: 10.1109/tpel.2002.807099
Google Scholar
[3]
Patella, A. Prodic´, A. Zirger, D. Maksimovic´, Highfrequency digital PWM controller IC for DC–DC converters, IEEE Transactions on Power Electronics 18 (2003).
DOI: 10.1109/tpel.2002.807121
Google Scholar
[4]
R. Ramos, X. Roset, A. Manuel, Implementation of fuzzy logic controller for DC/DC converters using field programmable gate array, in: Proc. 17th IEEE Instrumentation and Measurement Technology Conference, vol. 1, (2001).
DOI: 10.1109/imtc.2000.846846
Google Scholar
[5]
T. Ide, T. Yokoyama, A study of deadbeat control for three phase PWM inverter using FPGA based hardware controller, in: Proc. IEEE 35th Annual Power Electronics Specialists Conference, vol. 1, (2009).
DOI: 10.1109/pesc.2004.1355712
Google Scholar
[6]
R. Ruelland, G. Gateau, T. Meynard, J. Hapiot, Design of FPGA-based emulator for series multicell converters using co-simulation tools, IEEE Transactions on Power Electronics 18 (2004).
DOI: 10.1109/tpel.2002.807104
Google Scholar
[7]
R. Ramos, D. Biel, E. Fossas, F. Guinjoan, A fixedfrequency quasi-sliding control algorithm: application to power inverters design by means of FPGA implementation, IEEE Transactions on Power Electronics 18 (2010).
DOI: 10.1109/tpel.2002.807164
Google Scholar
[8]
S. Jung, M. Chang, J. Jyang, L. Yeh, Y. Tzou, Design and implementation of an FPGA-based control IC for ACvoltage regulation, IEEE Transactions on Power Electronics 14 (2009).
DOI: 10.1109/63.761696
Google Scholar
[9]
M.M. Islam, D. Allee, S. Konasani, A. Rodriguez, A lowcost digital controller for a switching DC converter with improved voltage regulation, IEEE Power Electronics Letters2 (2006).
DOI: 10.1109/lpel.2004.840256
Google Scholar
[10]
Cadenas, G. Megson, A clocking technique for FPGA pipelined designs, Journal of Systems Architecture 50 (2007).
DOI: 10.1016/j.sysarc.2004.04.001
Google Scholar
[11]
Brian von Herzen, Signal processing at 250 MHz using highperformance FPGA, IEEE Transactions on VLSI Systems 6 1998M. King, B. Zhu, and S. Tang, Optimal path planning, Mobile Robots, vol. 8, no. 2, pp.520-531, March (2001).
Google Scholar