Using Perturbation FEM Compute the IC Interconnect Parasitic Capacitances Considering Process Variation

Abstract:

In present IC design, the process variation such as the litho distortion has made the accurate extraction of parasitic capacitances of interconnects become more difficult. One of the problems is the generation of some small deformation including small angle, which makes it difficult to mesh generation when using 3D FEM solver, and the scale of the equation becomes larger. This paper uses the FEM with the perturbation to deal with the issue. We first build the matrix equation with the nominal geometry parameters, and then add the perturbation terms by using the derivative of the matrix and the dimension changes of the distorted conductors. The pertubated system equation is then solved to get the capacitances. The result shows that the method provides accurate capacitances with less CPU time and memory.

• Periodical: Advanced Materials Research (Volumes 301-303)
• Pages: 303-309
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.301-303.303
• Online since: July 2011
• Authors: Hui Qu, Xiao Yu Xu, Zhuo Xiang Ren
• Keywords: Integrated Circuit (IC) Parasitic Extraction, Perturbation FEM, Process Variation

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