A Vernier Delay Line for Time Interval Measurement
This paper presents a Vernier Delay Line (VDL) for time interval measurement. A dedicated multiplexer is inserted into each stage of the proposed VDL. As a result, the D-flip-flops in each stage can be served as a large delay cell as well as a traditional arbiter. Moreover, the proposed interface circuit can save time residue out for further fine granularity measurement. Experimental results show that the proposed VDL achieves a 30ns measurement range with 6600 transistors.
Riza Esa and Yanwen Wu
X. G. Wang et al., "A Vernier Delay Line for Time Interval Measurement", Advanced Materials Research, Vols. 301-303, pp. 995-1000, 2011