A Vernier Delay Line for Time Interval Measurement

Abstract:

This paper presents a Vernier Delay Line (VDL) for time interval measurement. A dedicated multiplexer is inserted into each stage of the proposed VDL. As a result, the D-flip-flops in each stage can be served as a large delay cell as well as a traditional arbiter. Moreover, the proposed interface circuit can save time residue out for further fine granularity measurement. Experimental results show that the proposed VDL achieves a 30ns measurement range with 6600 transistors.

• Periodical: Advanced Materials Research (Volumes 301-303)
• Pages: 995-1000
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.301-303.995
• Online since: July 2011
• Authors: Xin Gang Wang, Fei Wang, Hai Gang Yang
• Keywords: Large Measurement Range, Time Interval Measurement, Vernier Delay Line (VDL)

References

[1] E. R. Ruotsalainen, T. Rahkonen and J. Kostamovaara: An Integrated Time-to-Digital Converter With 30-ps single-shot precision, IEEE Journal of Solid-State Circuits, Vol. 35, no. 10(2000), pp.1507-1510.

DOI: 10.1109/4.871330

[2] M. A. Abas, G. Russell and D. J. Kinniment: Embedded High-Resolution Delay Measurement System Using Time Amplification, IET Comput. Digit. Tech. (2007), pp.77-86.

DOI: 10.1049/iet-cdt:20060099

[5] R.J. Ong, J.T. Dawley and P.G. Clem: submitted to Journal of Materials Research (2003).

[3] S. Y. Jiang, K. H. Cheng and P. Y. Jian: A 2. 5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver, IEEE Transactions on VLSI Systems, Vol. 17, no. 12(2009), pp.1698-1708.

DOI: 10.1109/tvlsi.2008.2006476

[4] K. H. Cheng, J. C. Liu, C. Y. Chang, S. Y. Jiang and K. W. Hong: Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator, IEEE Transactions on VLSI Systems(2010).

DOI: 10.1109/tvlsi.2010.2052377

[5] S. K. Lee, Y. H. Seo, H. J. Park and J. Y. Sim: A 1 GHz ADPLL With a 1. 25ps Minimum-Resolution Sub-Exponent TDC in 0. 18um CMOS, IEEE Journal of Solid-State Circuits, Vol. 45, no. 12(2010), pp.2874-2881.

DOI: 10.1109/jssc.2010.2077110

[6] J. Rivoir: Fully-digital time-to-digital converter for ATE with autonomous calibration, in Proc. IEEE Int. Test Conf. (2006), p.1–10.

DOI: 10.1109/test.2006.297713

[7] J. Yu, F.F. Dai, R. C. Jaeger: A 12-Bit Vernier Ring Time-to-Digital Converter in 0. 13 um CMOS Technology, IEEE Journal of Solid-State Circuits, Vol. 45, no. 4(2010), pp.830-842.

DOI: 10.1109/jssc.2010.2040306

[8] P. Dudek, S. Szczepanski and J. V. Hatfield: A High-Resolution CMOS Time-to-Digital Converter Utilizing a Vernier Delay Line, IEEE Journal of Solid-State Circuits, Vol. 35, no. 2(2000), pp.240-247.

DOI: 10.1109/4.823449

[9] T. Hashimoto, H. Yamazaki, A. Muramatsu, T. Sato and A. Inoue: Time-to-Digital Converter with Vernier Delay Mismatch Compensation for High Resolution On-Die Clock Jitter Measurement, Symposium on VLSI Circuits Digest of Technical Papers(2008).

DOI: 10.1109/vlsic.2008.4585992

[10] G. H. Li and H. P. Chou: A High-Resolution Time-to-Digital Converter Using Two-Level Vernier Delay Line Technique, IEEE Nuclear Science Symposium Conference(2007), pp.276-280.

DOI: 10.1109/nssmic.2007.4436330