In nano-like or nano-regime trench DRAM products, the product yield usually determines the marketing competition. Due to active area (AA) layer shift in lithography process, the cell leakage and the contact resistance at the source terminal of a cell transistor are increased. These factors will deteriorate the cell integrity in charging and access functions. To monitor this inferiority from lithography deviation, an improved Kelvin measurement and a novel pattern design were recommended. The yield improvement with this technology was really conspicuous.