Design of the Underwater Acoustic Signal Acquisition System Based on the Pipelined Twin-AD

Abstract:

In order to improve the accuracy of the underwater acoustic detection effectively, the digital signal acquisition circuxcA`\\it is a necessary deceive, which must have enough high data acquisition rate. Therefore the high frequency operating clock is employed in the traditional digital signal acquisition circuit. However, the high frequency operating clock will bring troubles to the design of hardware and software, and the power consumption and interference of the system are both increased. According to the principle of the pipelined system, the operation of AD deceive is divided into two process, including the conversion starting and data reading. The FPGA is employed to produce control signals which make twin-AD work in proper state. The design of the underwater acoustic signal acquisition system based on the pipelined twin-AD is presented here. On the base of the system design, simulation, implementation, the hardware experiments are completed. The results show: driven by the operating clock with same frequency, the underwater acoustic signal acquisition system based on the pipelined twin-AD can obtain the acquisition rate which is twice as the traditional data acquisition system.

• Periodical: Advanced Materials Research (Volumes 383-390)
• Pages: 497-502
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.383-390.497
• Online since: November 2011
• Authors: Guo Ku Zhao, Shu Shi Ning, Zhao Wei Cai, Ze Qian Xu
• Keywords: Field-Programmable Gate Array (FPGA), Pipelined, Signal Acquisition, Twin-AD, Underwater Acoustic

References

[1] LI Qihu, Advances of research work in underwater acoustics, Acta Acustica. vol. 26, Jul. 2001, pp.295-301.

[2] Tong Ziquan, Jia Jun, The system design of the high speed data aequisition based on FPGA, Foreign Electronic Measurement Technology. Dec. 2008, pp.30-32.

[3] LI Wei, GAO Zhi-hong, Design of High-speed Data Acquisition Card Based on CPLD400MHz, MECHANICAL ENGINEERING & AUTOMATION. Jun. 2009, pp.164-167.

[4] LAI Zhao-qing, PAN Ming, XU Yong, ZHANG Hui, The Design- implementation of embedded five Stage Pipeline CPU Core, Microcomputer Information. vol. 24, Oct. 2008, pp.32-34.

[5] Xu Zhijun, Xu Guanghui, The design and application of the CPLD/FPGA, Beijing: Publishing House of Electronics industry, Jan. (2002).

[6] Texas Instruments, Inc. 8-Bit, 60MHz Sampling ANALOG-TO-DIGITAL CONVERTER ADS830, (2001).

[7] Zhang Yang, Chen Jiasheng, Test Signal Generator With VGA Interface Based on SOPC, Journal of Nanjing Normal University. vol. 8, Jun. 2008, pp.78-80.

[8] Cypress Semiconductor Corporation. EZ-USB FX2 technical reference manual, Version2. (2003).