FPGA Implementation of an Error Detection and Correction Algorithm in Mode S-Based ADS-B System

Jian Hong Zhou; Chao Zhang; Xiao Bin Liu

doi:10.4028/www.scientific.net/AMR.403-408.1839

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 403-408FPGA Implementation of an Error Detection and...

FPGA Implementation of an Error Detection and Correction Algorithm in Mode S-Based ADS-B System

Abstract:

“ADS-B Messages” transmitted on 1090MHz are the Mode S Extended Squitters. When a Mode A/C fruit interferes with a mode S Extended Squitter, some of ADS-B signals may be received in error. These errors need to be corrected by some correction methods. To solve this problem, an error detection and correction algorithm using cyclic redundancy check (CRC) based on bit and confidence declaration is proposed in this paper. Then, the proposed algorithm using the Verilog hardware description language is verified by MODELSIM joint ISE simulation and realized on Field Programmable Gate Array (FPGA) based on ADS-B system. The results show that the algorithm can effective detect and correct data transmission error, which effective advances the reliability of the signal transmission for ADS-B system.

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Periodical:

Advanced Materials Research (Volumes 403-408)

Pages:

1839-1844

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.403-408.1839

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Online since:

November 2011

Authors:

Jian Hong Zhou, Chao Zhang, Xiao Bin Liu

Keywords:

ADS-B System, Bit and Confidence Declaration, Correction, CRC, Error Detection

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