10Gb/s RS-BCH Concatenated Encoder with Pipelined Strategies for Fiber Communication

Zheng Song; Qing Sheng Hu

doi:10.4028/www.scientific.net/AMR.429.154

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 42910Gb/s RS-BCH Concatenated Encoder with Pipelined...

10Gb/s RS-BCH Concatenated Encoder with Pipelined Strategies for Fiber Communication

Abstract:

This paper presents a 10Gb/s concatenated encoder compatible with the protocol of G.975. To achieve the high data rate, 8 RS encoders work based on the pipelined pattern. After the interleaving realized with 8 RAM blocks, the output of RS encoders are sent to 64 BCH encoders which work parallel. This concatenated encoder has been implemented in Xilinx Vertex5 FPGA, and the measurement results show that the data rate of 10Gb/b can be realized under the working frequency of 156MHz. About 9711 registers, 6984 LUTs and 40 Block-RAMs are utilized for the whole encoder.

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Periodical:

Advanced Materials Research (Volume 429)

Pages:

154-158

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.429.154

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Online since:

January 2012

Authors:

Zheng Song, Qing Sheng Hu

Keywords:

BCH Encoder, Concatenated Code, Pipeline, RS Encoder

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