Implementation of 10-Gb/s Parallel BCH Decoder Based on Virtex-5 FPGA

Zhang Qin; Qing Sheng Hu

doi:10.4028/www.scientific.net/AMR.429.159

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 429Implementation of 10-Gb/s Parallel BCH Decoder...

Implementation of 10-Gb/s Parallel BCH Decoder Based on Virtex-5 FPGA

Abstract:

This paper presents a design of 10Gb/s BCH decoder which is compatible with the protocol of G.975 and can be applied in optical fiber communication. The main blocks of this decoder include syndrome calculator, key-equation solver, Chien search and error correction. In order to achieve high speed, 8-bit parallel syndrome calculator and Chien search block are adopted. By sharing the key-equation solver, the numb er of key-equation solver is reduced and the hardware resources are saved. This decoder has been implemented in Virtex-5 FPGA and the verification results show that the decoder can work properly under the clock of 166MHz and the data rate can be up to 10Gb/s.

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Periodical:

Advanced Materials Research (Volume 429)

Pages:

159-164

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.429.159

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Online since:

January 2012

Authors:

Zhang Qin, Qing Sheng Hu

Keywords:

BCH Decoder, High-Speed, Parallel Structure, Pipeline

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References

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