A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application

Cao Yu; Min Su Kim; Hyung Chul Kim; Youn Goo Yang

doi:10.4028/www.scientific.net/AMR.457-458.1178

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 457-458A Low Power PFD and Dual Mode CP with Small...

A Low Power PFD and Dual Mode CP with Small Current Mismatch for PLL Application

Abstract:

A high speed Phase-Frequency Detector (PFD) and Charge Pump (CP) are implemented using 0.13µm CMOS process with 1.2 V supply. The PFD is implemented with TSPC (True Single-Phase Clock) and positive edge triggered D flip-flop. Its polarity can be changed by setting the port. The dead zone problem is solved using an additional reset time. A single charge pump is implemented with two compensators. Dual mode CP design makes the charge pump much more flexible in applications. The current mismatch for the two modes is below 4.9 % within the voltage range of from 0.2 to 1.0 V.

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Periodical:

Advanced Materials Research (Volumes 457-458)

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1178-1182

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.457-458.1178

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Online since:

January 2012

Authors:

Cao Yu, Min Su Kim, Hyung Chul Kim, Youn Goo Yang

Keywords:

CP, PFD, PLL

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References

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