Design of UART with CRC Check Based on FPGA

Abstract:

In order to realize the accurate serial communication, a simple and practical scheme for URAT design and implementation was put forward based on the analysis of CRC generation algorithm. The reliability of serial communication can be improved by adding CRC into the asynchronous serial communication. The CRC checksum module is achieved with Verilog language on the basis of FPGA and obtained consistence between the results of simulation and theoretical analysis. Therefore, the expected design target was met, and the communication speed and efficiency was improved.

• Periodical: Advanced Materials Research (Volumes 490-495)
• Pages: 1241-1245
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.490-495.1241
• Online since: March 2012
• Authors: Xiao Rong Tong, Zhong Biao Sheng
• Keywords: CRC-5, Error Control, Field-Programmable Gate Array (FPGA), UART

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