Design of Finite State Machine Based on VHDL

Zhi Ping Zhu; Yong Qin Liu; Hong Sheng; Feng Ye

doi:10.4028/www.scientific.net/AMR.529.335

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 529Design of Finite State Machine Based on VHDL

Design of Finite State Machine Based on VHDL

Abstract:

Different encoding scheme and method for process description of state machine are analyzed in detail, and the advantages and disadvantages of each are pointed out. The general state machine design method is given by a specific example program, according to the actual need, designers can choose different encoding scheme and method for process description to design.

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Periodical:

Advanced Materials Research (Volume 529)

Pages:

335-338

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.529.335

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Online since:

June 2012

Authors:

Zhi Ping Zhu, Yong Qin Liu, Hong Sheng, Feng Ye

Keywords:

Encoding Scheme, Finite State Machine, Process Description, VHDL

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