Design of Real-Time Image Collecting Module Based on FPGA

Abstract:

A new pixel collecting interface board based on FPGA is designed, it is a part of conveyer belt’s fault detection device. The previous system’s controller chip CPLD is replaced by FPGA, the memory FIFO chips are replaced by SRAM, the chip CY7C68013 is chosen as the USB 2.0 controller and works in Slave FIFO transmission mode. The firmware program and application program are compiled to transmit data. The Chipscope Pro Tools are used in the system to debug online, and the correctness of data transmission can be analyzed and verified. The experimental results demonstrate that the new pixel collecting interface board has the advantage of high-speed data acquisition, and can transmit data in real time and correctly. It also has a good scalability and can be used into other high-speed acquisition systems.

• Periodical: Advanced Materials Research (Volumes 532-533)
• Pages: 1095-1099
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.532-533.1095
• Online since: June 2012
• Authors: Jiang Wei Wang, Mu Yan Ma, Jun Min Leng
• Keywords: Collecting Board, Field-Programmable Gate Array (FPGA), Slave FIFO, USB 2.0

References

[1] Cypress Semiconductor: EZ-USB Technical Reference Manual(2004), p.2-p.15.

[2] Xilinx: ChipScope Pro 12. 1 Software and Cores User Guide(2010), p.7-p.14.

[3] Xilinx: Device Package User Guide(2007), p.5-p.8.

[4] Xilinx: Spartan-3 FPGA Family Complete Data Sheet(2004), p.35-p.48.

[5] Information on http: /www. cypress. com.

[6] Yang Hua, in: The Research of Real-Time Image Acquisition & Processing System Based on FPGA, edited by Changchun University(2005).

[7] Gong Tao, in: The Design of Collecting and Processing System Based on FPGA, edited by Wuhan University(2005).

[8] Xu Hong-zhe, Wang Jian-xin, Chao Lu-meng, in: The Design and Implementation of Plate-profile information collecting and processing system based on FPGA, edited by ICCSIT(2010).

DOI: 10.1109/iccsit.2010.5564638