A Circuit for Robustness Enhancement of the Subthreshold SRAM Bitcell in 65nm Technology

Abstract:

This paper describes a circuit which can enhance the robustness of the subthreshold 6T SRAM bitcell. The proposed circuit can dynamically adjust the body voltages of the PMOS transistors in order to enhance the robustness of the subthreshold 6T SRAM bitcell by detecting the variation of the threshold voltage. The simulation results under 300mV in 65nm technology demonstrate that the mean values of the read and hold static noise margin (SNM) of the subthreshold 6T SRAM bitcell have been improved by 18% and 0.7%, respectively, meanwhile the standard values of the read and hold SNM have improved by 82% and 29.4%, respectively, by adopting the proposed circuit. Moreover, the proposed circuit functions well in a wide range of supply voltage from 0.2V to 0.5V.

• Periodical: Advanced Materials Research (Volumes 542-543)
• Pages: 1001-1006
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.542-543.1001
• Online since: June 2012
• Authors: Bai Tao Lv, Rui Xing Li, Jiafeng Zhu, Na Bai, Xiu Long Wu
• Keywords: Bitcell, SRAM, Stability, Subthreshold

References

[1] P. Yu, J. Pineda de Gyvez, H. Corporaal, and H. Yajun, An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub/Near Threshold Supply Voltage, Solid-State Circuits, IEEE Journal of, vol. 45 (2010), pp.668-680.

DOI: 10.1109/jssc.2009.2039684

[2] H. Fuketa, D. Kuroda, M. Hashimoto, and T. Onoye, An Average-Performance-Oriented Subthreshold Processor Self-Timed by Memory Read Completion, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 58 (2011), pp.299-303.

DOI: 10.1109/tcsii.2011.2149110

[3] M. Wei-Hsiang, J. C. Kao, V. S. Sathe, and M. C. Papaefthymiou, 187 MHz Subthreshold-Supply Charge-Recovery FIR, Solid-State Circuits, IEEE Journal of, vol. 45 (2010), pp.793-803.

DOI: 10.1109/jssc.2010.2042247

[4] Z. Bo, S. Pant, L. Nazhandali, S. Hanson, J. Olson, A. Reeves, M. Minuth, R. Helfand, T. Austin, D. Sylvester, and D. Blaauw, Energy-Efficient Subthreshold Processor Design, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 17 (2009).

DOI: 10.1109/tvlsi.2008.2007564

[5] C. Ik Joon, K. Jae-Joon, S. P. Park, and K. Roy, A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS, Solid-State Circuits, IEEE Journal of, vol. 44 (2009), pp.650-658.

DOI: 10.1109/jssc.2008.2011972

[6] C. Meng-Fan, C. Shi-Wei, C. Po-Wei, and W. Wei-Cheng, A 130 mV SRAM With Expanded Write and Read Margins for Subthreshold Applications, Solid-State Circuits, IEEE Journal of, vol. 46 (2011), pp.520-529.

DOI: 10.1109/jssc.2010.2091321

[7] H. Mostafa, M. H. Anis, and M. Elmasry, Analytical Soft Error Models Accounting for Die-to-Die and Within-Die Variations in Sub-Threshold SRAM Cells, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 19 (2011), pp.182-195.

DOI: 10.1109/tvlsi.2009.2033697

[8] M. Meterelliyoz, P. Song, F. Stellari, J. P. Kulkarni, and K. Roy, Characterization of Random Process Variations Using Ultralow-Power, High-Sensitivity, Bias-Free Sub-Threshold Process Sensor, Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 57 (2010).

DOI: 10.1109/tcsi.2009.2037449

[9] F. Moradi, D. Wisland, Y. Berg, S. Aunet, and C. Tuan Vu, Process variations in sub-threshold SRAM cells in 65nm CMOS, in Microelectronics (ICM), 2010 International Conference on (2010), pp.371-374.

DOI: 10.1109/icm.2010.5696164

[10] J. P. Kulkarni and K. Roy, Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. PP (2011), pp.1-1.

DOI: 10.1109/tvlsi.2010.2100834

[11] K. Tae-Hyoung, J. Liu, and C. H. Kim, An 8T Subthreshold SRAM Cell Utilizing Reverse Short Channel Effect for Write Margin and Read Performance Improvement, in Custom Integrated Circuits Conference (2007), pp.241-244.

DOI: 10.1109/cicc.2007.4405723

[12] N. Bai, C. Xuan, J. Yang, and L. Shi, A differential read subthreshold SRAM bitcell with self-adaptive leakage cut off scheme, in SOC Conference (SOCC), 2010 IEEE International (2010), pp.455-460.

DOI: 10.1109/socc.2010.5784678

[13] P. Yu, J. de Jesus Pineda de Gyvez, H. Corporaal, and H. Yajun, Vt balancing and device sizing towards high yield of sub-threshold static logic gates, in Low Power Electronics and Design (ISLPED), 2007 ACM/IEEE International Symposium on (2007).

DOI: 10.1145/1283780.1283857