A 16Kb SRAM with Programmable Replica Bitlines for Dynamic Voltage Scaling Systems

Abstract:

The SRAM applied to dynamic voltage scaling systems has a problem that the differential voltage of the bitlines (ΔV_BL) increases as the supply voltage rises with the conventional replica bitlines technique, and the increased ΔV_BL degrades the SRAM performance and dissipates more power. In this paper, a programmable replica bitlines technique is presented to resolve the problem. With the new technique we acquired bitline discharge time reduction up to 25.3% at the cost of 0.6% area penalty in a 16Kb SRAM. The 16Kb SRAM test chip is fabricated by using 65nm low leakage technology. Testing results show that the maximum operational frequency of the SRAM is improved from 4.3% to 9.5% under the voltage range of 0.8V~1.4V comparing with the conventional one. The operating frequency of the SRAM with proposed technique is from 440MHz at 0.8V to 1.62GHz at1.4V.

• Periodical: Advanced Materials Research (Volumes 542-543)
• Pages: 416-422
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.542-543.416
• Online since: June 2012
• Authors: Ming Qiang Qiu, Na Bai, Jian Meng, Jun Ning Chen
• Keywords: Dynamic Voltage Scaling, Replica Bitlines Technique, SAE, Sense Amplifier (SA), SRAM

References

[1] K. Jungsoo, et al., "Program Phase-Aware Dynamic Voltage Scaling Under Variable Computational Workload and Memory Stall Environment," Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, vol. 30, pp.110-123, 2011.

DOI: 10.1109/tcad.2010.2068630

[2] J. Lee, et al., "Application-support Particle Filter for Dynamic Voltage Scaling of Multimedia Applications," Computers, IEEE Transactions on, vol. PP, pp.1-1, 2011.

[3] Y. Niki, et al., "A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers," Solid-State Circuits, IEEE Journal of, vol. 46, pp.2545-2551, 2011.

DOI: 10.1109/jssc.2011.2164294

[4] B. S. Amrutur and M. A. Horowitz, "A replica technique for wordline and sense control in low-power SRAM's," Solid-State Circuits, IEEE Journal of, vol. 33, pp.1208-1219, 1998.

DOI: 10.1109/4.705359

[5] S. Komatsu, et al., "A 40-nm low-power SRAM with multi-stage replica-bitline technique for reducing timing variation," in Custom Integrated Circuits Conference, 2009. CICC '09. IEEE, 2009, pp.701-704.

DOI: 10.1109/cicc.2009.5280731

[6] K. Osada, et al., "Universal-Vdd 0.65-2.0-V 32-kB cache using a voltage-adapted timing-generation scheme and a lithographically symmetrical cell," Solid-State Circuits, IEEE Journal of, vol. 36, pp.1738-1744, 2001.

DOI: 10.1109/4.962296

[7] L. Chang, et al., "An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches," Solid-State Circuits, IEEE Journal of, vol. 43, pp.956-963, 2008.

DOI: 10.1109/jssc.2007.917509

[8] K. Tae-Hyoung, et al., "A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode," Solid-State Circuits, IEEE Journal of, vol. 44, pp.1785-1795, 2009.

DOI: 10.1109/jssc.2009.2020201

[9] S. M. Cheng-Hung Lo, IEEE, and Shi-Yu Huang, Member, IEEE, "P-P-N Based 10T SRAM Cell for Low-Leakage and Resilient Subthreshold Operation," IEEE JOURNAL OF SOLID-STATE CIRCUITS, pp.695-704, 2011.

DOI: 10.1109/jssc.2010.2102571