The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

Bao Feng Zhang; De Hu Man; Jun Chao Zhu

doi:10.4028/www.scientific.net/AMR.571.534

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 571The Design and Implementation of Parallel...

The Design and Implementation of Parallel Distributed Algorithm FIR Filter Based on FPGA

Abstract:

The article proposed a new method for implementing linear phase FIR filter based on FPGA. For the key to implementing the FIR filter on FPGA—multiply-add operation, a parallel distributed algorithm was presented, which is based on LUT. The designed file was described with VHDL and realized on Altera’s field programmable gate array (FPGA), giving the design method. The experimental results indicated that the system can run stably at 120MHz or more, which can meet the requirements of signal processing for real-time.

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Periodical:

Advanced Materials Research (Volume 571)

Pages:

534-537

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.571.534

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Online since:

September 2012

Authors:

Bao Feng Zhang, De Hu Man, Jun Chao Zhu

Keywords:

DA (Distributed Algorithm), Field-Programmable Gate Array (FPGA), FIR Digital Filter, LUT, Real-Time

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References

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