Source-End Layout Influences on MOSFET ESD Protection Devices in a 0.35um 5V Process

Shen Li Chen; Min Hua Lee; Tzung Shian Wu

doi:10.4028/www.scientific.net/AMR.694-697.1454

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Source-End Layout Influences on MOSFET ESD Protection Devices in a 0.35um 5V Process
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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 694-697Source-End Layout Influences on MOSFET ESD...

Source-End Layout Influences on MOSFET ESD Protection Devices in a 0.35um 5V Process

Abstract:

An nMOS transistor in input/output pad as the ESD protection element is usually in the form of multi-finger layout. This paper will show simple but effective ways to improve an nMOSFET’s ESD robustness or LU immunity for use in I/O pads, i.e., the source-end layout influences on the protection components in ESD/LU capabilities of the input/output pads will be investigated. In other words, they are used to increase the effective ESD or LU capability of the ESD protection elements. Here, the different source-end layout types will be carried out the important snapback parameters. We focus on exploring the secondary breakdown current (I_t2) and holding voltage (V_h) for the ESD discharge capability and the latch-up immunity, hopefully, it does effectively enhance ESD/LU robustness.