WLVT: A Static Wear-Leveling Algorithm with Variable Threshold

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NAND flash memory has been successfully employed in storage system due to its advantages such as performance, resistance, and capacity. NAND flash memory based solid state disk (SSD) has started to replace disk in numerous environments. However, the poor endurance offered by these SSDs continues to be their key shortcoming. To improve SSD endurance, we propose a static wear-leveling algorithm with variable threshold (WLVT). In contrast with traditional algorithm with fixed threshold, WLVT adjusts the value of threshold, so that each block can simultaneously reach the erasure times that the manufacturer gives when life of SSD is over. Therefore, available erasure time of each block will be fully utilized when SSD fails. Experimental results show that the endurance of the SSD is significantly improved.

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Advanced Materials Research (Volumes 756-759)

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3131-3135

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September 2013

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© 2013 Trans Tech Publications Ltd. All Rights Reserved

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[1] Flash Cache Memory Puts Robson in the Middle. Intel.

Google Scholar

[2] S. Lee, B. Moon, C. Park, J. Kim, and S. Kim. A case for flash memory SSD in enterprise database applications. Proc. Int. Conf. on Management of Data (SIGMOD), pp.1075-1086, (2008).

DOI: 10.1145/1376616.1376723

Google Scholar

[3] BAN A. Wear leveling of static areas in flash memory: US,0184432EP.2002-12-05.

Google Scholar

[4] ASSAR M. Flash memory mass storage architecture: US,5388083. 1995-02-07.

Google Scholar

[5] LEE C C. System and method for managing blocks in flash memory: US, 0204187. 2005-09-15.

Google Scholar

[6] LOFGREN&Wear leveling techniques for flash EEPROM systems: US, 6230233EP. 2001-05-08.

Google Scholar

[7] CHANG R. wear. 1eveling in non-volatile storage systems: US, 6985992[P]. 2006-01-10.

Google Scholar

[8] CHANG Yuanhao, HSIEH J W, KUO T W. Endurance enhancement of flash-memory storage systems: an efficient static wear leveling design, Proceedings of the 2007 Design Automation Conference. San Diego: ACM Press, 2007: 212-217.

Google Scholar

[9] CHANG Lipin. On efficient wear leveling for large-scale flash-memory storage systems, Proceedings of the 2007 ACM Symposium on Applied Computing. Seoul: ACM Press, 2007: 1126-1130.

DOI: 10.1145/1244002.1244248

Google Scholar

[10] N. Agrawal, V. Prabhakaran, T. Wobber, J. Davis, M. Manasse, and R. Panigrahy, Design Tradeoffs for SSD Performance, Proceedings of the USENIX Annual Technical Conference, pp.57-70, (2008).

Google Scholar

[11] S. Boboila and P. Desnoyers, Write Endurance in Flash Drives: Measurements and Analysis, Proceedings of the 8th USENIX Conference on File and Storage Technologies (FAST), (2010).

Google Scholar

[12] Increasing Flash Solid State Disk Reliability. Technical report, SiliconSystems, Apr (2005).

Google Scholar

[13] S. Gurumurthi, A. Sivasubramaniam, and V.K. Natarajan, Disk Drive Roadmap from the Thermal Perspective: A Case for Dynamic Thermal Management, Proceedings of the 32nd International Symposium. Computer Architecture (ISCA), pp.38-49, (2005).

DOI: 10.1109/isca.2005.24

Google Scholar

[14] F. Chen, D.A. Koufaty, and X. Zhang, Understanding Intrinsic Characteristics and System Implications Of Flash Memory based Solid State Drives, Proceedings of the Eleventh International Joint Conference of Measurement and Modeling of Computer Systems (SIGMETRICS), pp.181-192, (2009).

DOI: 10.1145/1555349.1555371

Google Scholar

[15] Y. Hu, H. Jiang, D. Feng, L. Tian, S. Zhang, J. Liu, W. Tong, Y. Qin, and L. Wang, Achieving page-mapping FTL performance at block-mapping FTL cost by hiding address translation, Proceedings of the IEEE 26th Symposium on Mass Storage Systems and Technologies (MSST), pp.1-12, (2010).

DOI: 10.1109/msst.2010.5496970

Google Scholar

[16] D. Jung, J-U Kang, H. Jo, J. Kim, and J. Lee, Superblock FTL: A Superblock-Based Flash Translation Layer with a Hybrid Address Translation Scheme, ACM Transactions on Embedded Computing Systems, Volume 9, Issue 4, March (2010).

DOI: 10.1145/1721695.1721706

Google Scholar

[17] J.Y. Shin, Z.L. Xia, N. Y Xu, R. Gao, X.F. Cai, S. Maeng, and F.H. Hsu, FTL design exploration in reconfigurable high-performance SSD for server applications, Proceedings of the 23rd International Conference of Supercomputing, pp.338-349, (2009).

DOI: 10.1145/1542275.1542324

Google Scholar