Design of Low Voltage Low Power ADC for WSN Node

Abstract:

This paper presents a low power low voltage 7bit 16MS/s SAR ADC (successive approximation register analog-to-digital converter) for the application of ZigBee receiver. The proposed 7-bit ADC is designed and simulated in 180nm RF CMOS technology. Post simulation results show that at 1.0-V supply and 16 MS/s, the ADC achieves a SNDR (signal-to-noise-and-distortion ratio) and SFDR (Spurious Free Dynamic Range) are 43.6dB, 57.4dB respectively. The total power dissipation is 228μW, and it occupies a chip area of 0.525 mm². It results in a figure-of-merit (FOM) of 0.11pJ/step.

• Periodical: Advanced Materials Research (Volumes 760-762)
• Pages: 561-566
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.760-762.561
• Online since: September 2013
• Authors: Si Kui Ren, Zhi Qun Li
• Keywords: Analog-to-Digital Converter (ADC), Low-Power, Low-Voltage, SAR, ZigBee

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