A Novel Design of PIE Decoding with Multiple CRC Circuit for RFID Tag

Feng Ying Huang; Jun Wang; Yu Sen Xu; Ji Wei Huang

doi:10.4028/www.scientific.net/AMR.816-817.957

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HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 816-817A Novel Design of PIE Decoding with Multiple CRC...

A Novel Design of PIE Decoding with Multiple CRC Circuit for RFID Tag

Abstract:

This paper proposes a new synchronized serial-parallel CRC(Cycle Redundancy Check) with PIE(Pulse Interval Encoding) decoding circuit for the UHF(Ultra-High Frequency) RFID(Radio Frequency Identification), which is based on the ISO/IEC 18000-6C standards protocol. The parallel algorithm of CRC circuit is derived, and the serial or parallel CRC circuit on RFID tag chip is evaluated in this paper. Finally, the designed circuit is simulated and analyzed on the FPGA platform. Simulation results show that the proposed circuit meets the communication requirement of the protocol and addresses the problem of low data processing rate of conventional serial CRC circuit, as well as implements 1 to 8 degree of parallelism of the parallel CRC circuit for UHF RFID.

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Periodical:

Advanced Materials Research (Volumes 816-817)

Pages:

957-961

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.816-817.957

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Online since:

September 2013

Authors:

Feng Ying Huang, Jun Wang, Yu Sen Xu, Ji Wei Huang

Keywords:

CRC, Field-Programmable Gate Array (FPGA), PIE Decoder, RFID

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References

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