Multi-CPU Parallel Computing System with Mixed Modes

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Abstract:

Multi-CPU[1] parallel computing system [2] with mixed modes is the product of parallel computing idea. Control system cannot guarantee real-time control performance due to limitation of computing speed while utilizing complex control algorithms, so operating efficiency of the system needs to be solved. High-speed computing [3] system is needed. Parallel algorithm [4][5] is an effective way to improve computing speed. Mixed-mode parallel computing system is a hardware platform with multiple parallel computing modes. Users can directly change the connecting mode between computing modules through jumper, and the diversity of communication modes provides solutions for various problems.

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Periodical:

Advanced Materials Research (Volumes 915-916)

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1175-1180

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Online since:

April 2014

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© 2014 Trans Tech Publications Ltd. All Rights Reserved

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[1] Liu, Huahai1, Wang, Pan, Research on multi-CPU and multi-GPU scalable parallel rendering on shared memory architecture, Proceedings of the 2012 International Conference on Computer Application and System Modeling, (2012) pp.1447-1450.

DOI: 10.2991/iccasm.2012.370

Google Scholar

[2] Duan, Zongtao; Lei, Tao; Fan, Haiwei, Parallel computing system for image intelligent processing, Information Technology Journal, Vol. 11, No3 (2012), pp.329-333.

DOI: 10.3923/itj.2012.329.333

Google Scholar

[3] Xu Jiatong, Li Xuegan, Parallel processing technology, Xian: xidian university publisher (1999).

Google Scholar

[4] Chi Xuebin, High performance parallel computing, The computer network information center of Chinese Academy of Sciences, (2005).

Google Scholar

[5] Yang Xiaosong, Lu Song, Mou Shengmei, The technology and panalysis of arallel computer and architecture, Beijing: Science Press (2009).

Google Scholar

[6] Mao Youju; Lu Yi; Liu Jiang; Dang, Mingrui, Scheme of optical interconnection for super high speed parallel computer, Chinese Optics Letters , Vol. 2, No11 (2004), pp.667-669.

Google Scholar

[7] Shao Beibei, Gong Guanghua, Understanding and practice of single chip microcomputer, Beijing: Beihang University press(2006), pp.93-100.

Google Scholar

[8] Zhao Jianlei, Gong Lei The 51 Series MCU development, Electronic Industry Press (2007), pp.66-88.

Google Scholar

[9] Zhao, Lei ; Chen, Geng ; Yu, Wenhua A novel enhancing technique for parallel FDTD method using processor affinity and NUMA policy, , Applied Computational Electromagnetics Society Journal , Vol. 27, No8 (2012), P638-645.

Google Scholar

[10] Park, Junyoung1, Hong, Injoon, A multi-granularity parallelism object recognition processor with content-aware fine-grained task scheduling, IEEE Symposium on Low-Power and High-Speed Chips - Proceedings for 2013 COOL Chips XVI (2013).

DOI: 10.1109/coolchips.2013.6547917

Google Scholar