Low Voltage FGMOS Four Quadrants Analog Multiplier

Abstract:

In this paper a low voltage FGMOS analog multiplier is proposed that uses a follower voltage flipped (FVF), which dominates its operation. In order to reduce the power supply of the multiplier, floating gate CMOS transistors (FGMOS) are used. Theoretical steps of the FVF design are presented together with its simulation. The output of the FVF is insensitive to the device parameters and is loaded with a resistive load. The multiplier design consists of two FVF cells, two current sensors FVF and one Gilbert cell multiplier. The results show that the proposed multiplied in a 0.13μm CMOS process exhibits significant benefits in terms of linearity, insensibility to device parameters, bandwidth and output impedance. The power supply is 0.8V and a power consumption of 181μW.

• Periodical: Advanced Materials Research (Volume 918)
• Pages: 313-318
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.918.313
• Online since: April 2014
• Authors: Jesús de la Cruz-Alejo*, L. Noe Oliva-Moreno
• Keywords: CMOS, Floating Gate, Follower Voltage Flipped, Low Voltage, Multiplier

References

[1] C. W. Kim, S. B. Park, Design and implementation of a new four quadrant MOS analog multiplier, Analog Integrated Circuits and Signal Processing, vol. 2, p.95–103, (1992).

DOI: 10.1007/bf00142410

[2] M. Gravati, M. Valle, G. Ferri, N. Guerrini, L. Reyes , A Novel Current-Mode Very Low Power Analog CMOS Four Quadrant Multiplier, Proc. ESSCIRC, Grenoble, France, (2005).

DOI: 10.1109/esscir.2005.1541668

[3] G. Han and E. Sanchez-Sinencio CMOS Transconductance multipliers: A Tutorial, IEEE Transactions on Circts. and Syst. 11: Analog and Digital signal Processing, Vol. 45, No. 12, December 98, pp.1550-1563.

DOI: 10.1109/82.746667

[4] Tanno, K., Matsumoto, H., Ishizuka, O., & Tang, Z: (1999). Simple CMOS voltage follower with resistive-load drivability. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, 46(2), 172-177.

DOI: 10.1109/82.752947

[5] Shibata, T. and Ohmi, T. (1992). A Functional MOS Transistor Featuring Gate-Level Weighted Sum and Threshold Operations,. IEEE Transactions on Electron Devices, Vol. 39, Issue 6, pp.1444-1455.

DOI: 10.1109/16.137325

[6] de la Cruz-Alejo, J., F. Gomez-Castaneda, and J. A. Moreno-Cadenas. New topology for a variable differential delay line using the FGMOS transistor., International Journal of Electronics  Vol 95, No. 12 (2008), pp.1305-1321.

DOI: 10.1080/00207210802492344

[7] de la Cruz-Alejo, Jesus, A. Santiago Medina-Vazquez, and L. Noe Oliva-Moreno. FGMOS four-quadrant analog multiplier., Electrical Engineering, Computing Science and Automatic Control (CCE), (2012).

DOI: 10.1109/iceee.2012.6421200

[8] T. Ochiai and H. Hatano, "DC Characteristic Simulation for Floating Gate Neuron MOS Circuits, Electronics Letters, Vol. 35, No. 18, Sept. (1999).

DOI: 10.1049/el:19991023