[6]
This work Type Digital Digital Digital Technology.
Google Scholar
13 µm Frequency 30 MHz-1 GHz 40-550 MHz 10 MHz-1 GHz VDD.
Google Scholar
[1]
5 V Lock time ≤42 cycles 134~14 cycles 20~12 cycles Power.
Google Scholar
[1]
5 mW(30 MHz).
Google Scholar
[12]
6 mW(550 MHz).
Google Scholar
[6]
4 mW(1 GHz) Conclusion A wide range fast-lock all digital delay locked loop is presented in this paper. A delay compensation circuit is used to detect PVT conditions after the tapped delay circuit is powered on, so that the series number of the shift register can be correctly preset and the large amount of phase difference is compensated. The DLL has fast settling time due to the effective delay compensation. The proposed technique has been implemented in a 0. 13 μm CMOS process. The DLL is jitter-immune and the power consumption is very low. Experimental results verify that this DLL is stable against process, voltage, and temperature variations. References.
DOI: 10.17760/d20002106
Google Scholar
[1]
G.W. Roberts, and M. Ali-Bakhshian, A brief introduction to time-to-digital and digital-to-time converters, IEEE Transactions on Circuits and Systems-II: Express Briefs. vol. 57, no. 3, Mar. 2010, pp.153-157.
DOI: 10.1109/tcsii.2010.2043382
Google Scholar
[2]
W. Liu, W. Li, P. Ren, C. Lin, S. Zhang, and Y. Wang, A PVT tolerant 10 to 500MHz all-digital phase-locked loop with coupled TDC and DCO, IEEE Journal of Solid-State Circuits. vol. 45, no. 2, Feb. 2010, pp.314-321.
DOI: 10.1109/jssc.2009.2038127
Google Scholar
[3]
W. -H. Chiu,Y. -H. Huang, and T. -H. Lin, A dynamic phase error compensation technique for fast-locking phase-locked loops, IEEE Journal of Solid-State Circuits. vol. 45, no. 6, Jun. 2010, pp.1137-1149.
DOI: 10.1109/jssc.2010.2046235
Google Scholar
[4]
B. Ye. A wide-range all digital DLL for multiphase clock generation, Microelectronics Journal. vol. 41, no. 7, Jun. 2010, pp.411-416.
DOI: 10.1016/j.mejo.2010.04.013
Google Scholar
[5]
L. Wang, L. Liu, and H. Chen, An implementation of fast-locking and wide-range 11-bit reversible SAR DLL, IEEE Transactions on Circuits and Systems-II: Express Briefs. vol. 57, no. 6, Jun. 2010, pp.421-425.
DOI: 10.1109/tcsii.2010.2048379
Google Scholar
[6]
R. -J. Yang and S. -I. Liu, A 40-550 MHz harmonic-free all-digital delay-locked loop using a variable SAR algorithm, IEEE Journal of Solid-State Circuits, vol. 42, no. 2.
DOI: 10.1109/jssc.2006.889381
Google Scholar