An Implementation of Wide-Range Digital Delay Locked Loop

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Abstract:

This paper presents an all digital delay-locked loop (DLL) to achieve wide range operation, fast lock and process immunity. To keep track of any potential phase problem caused by environmental variations, a delay compensation mechanism is employed. Utilizing the delay compensation controller (DCC), the proposed DLL can overcome the false-lock problem in conventional designs. It is fast locking because the DLL’s initial state can be detected by the delay compensation controller and the initial large phase difference can be eliminated. The proposed DLL is implemented in a 0.13μm CMOS process. The experimental result shows that the chip could work in a wide frequency range from 10 MHz to 1 GHz, with less than 20 cycles lock-in time, 10-ps delay resolution, and 6.4 mW at 1 GHz power dissipation.

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Advanced Materials Research (Volumes 945-949)

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2226-2229

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June 2014

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© 2014 Trans Tech Publications Ltd. All Rights Reserved

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[6] This work Type Digital Digital Digital Technology.

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13 µm.

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18 µm.

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13 µm Frequency 30 MHz-1 GHz 40-550 MHz 10 MHz-1 GHz VDD.

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[1] 2 V.

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[1] 8 V.

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[1] 5 V Lock time ≤42 cycles 134~14 cycles 20~12 cycles Power.

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[1] 5 mW(30 MHz).

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[12] 6 mW(550 MHz).

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[6] 4 mW(1 GHz) Conclusion A wide range fast-lock all digital delay locked loop is presented in this paper. A delay compensation circuit is used to detect PVT conditions after the tapped delay circuit is powered on, so that the series number of the shift register can be correctly preset and the large amount of phase difference is compensated. The DLL has fast settling time due to the effective delay compensation. The proposed technique has been implemented in a 0. 13 μm CMOS process. The DLL is jitter-immune and the power consumption is very low. Experimental results verify that this DLL is stable against process, voltage, and temperature variations. References.

DOI: 10.17760/d20002106

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