Design of Router Supporting Multiply Routing Algorithm for NoC

Zhan Peng Jiang; Rui Xu; Chang Chun Dong; Lin Hai Cui

doi:10.4028/www.scientific.net/AMR.981.431

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Simulation of FBG Wavelength Signal Demodulation Based on Sideband Filter
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Corrected Differential Evolution Particle Filter for Nonlinear Filtering
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Implementation of FFT Algorithm Based on IP Core
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Design of Router Supporting Multiply Routing Algorithm for NoC
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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 981Design of Router Supporting Multiply Routing...

Design of Router Supporting Multiply Routing Algorithm for NoC

Abstract:

Network on Chip(NoC)，a new proposed solution to solve global communication problem in complex System on Chip (SoC) design，has absorbed more and more researchers to do research in this area. Due to some distinct characteristics, NoC is different from both traditional off-chip network and traditional on-chip bus，and is facing with the huge design challenge. NoC router design is one of the most important issues in NoC system. The paper present a high-performance, low-latency two-stage pipelined router architecture suitable for NoC designs and providing a solution to irregular 2Dmesh topology for NoC. The key features of the proposed Mix Router are its suitability for 2Dmesh NoC topology and its capability of suorting both full-adaptive routing and deterministic routing algorithm.

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Periodical:

Advanced Materials Research (Volume 981)

Pages:

431-434

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.981.431

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Online since:

July 2014

Authors:

Zhan Peng Jiang*, Rui Xu, Chang Chun Dong, Lin Hai Cui

Keywords:

Multiply Routing Algorithm, NoC, Router

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