Design and Implementation of a RISC Processor on FPGA

Hui Jing Yang; Hao Fan; Huai Guo Dong

doi:10.4028/www.scientific.net/AMR.981.58

Paper Titles

The Nonlinearities of Memoryless Power Amplifier and Model of Predistorter
p.40

Low-Cost and Modularized Test Bench for Focal Plane Array
p.46

Design of Music Prescription for Music Electroacupuncture Instrument
p.50

The Analysis of Institutional Factors for Gain of EDFA
p.54

Design and Implementation of a RISC Processor on FPGA
p.58

The Modeling of OTFT and the Measuring of Small Signal Detection Circuit
p.62

A Bandgap Reference with Temperature Coefficient of 13.2 ppm/°C
p.66

CMOS Low Power Ring VCO Design
p.70

The Dual Sine Signal Generator Design Based on the Principle of Difference Frequency Filtering
p.74

HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 981Design and Implementation of a RISC Processor on...

Design and Implementation of a RISC Processor on FPGA

Abstract:

This paper targets the computer architecture courses and presents an Field Programmable Gate Array implementation of a RISC Processor via Verilog HDL design. It has 8-bit instruction words and 4 general purpose registers. It have two instruction formats. And it has been designed with Verilog HDL, synthesized using Quatus II 12.0, simulated using ModelSim simulator, and then implemented on Altera Cyclone IV FPGA that has 484 available Input/Output pins and 50MHz clock oscillator. The final overall simulation's experimental data verify the correctness of the processor.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Advanced Materials Research (Volume 981)

Pages:

58-61

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.981.58

Citation:

Cite this paper

Online since:

July 2014

Authors:

Hui Jing Yang, Hao Fan*, Huai Guo Dong

Keywords:

Control Unit, CPU, Processor, RISC, Verilog HDL

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] Michael Gschwind, Valentina Salapura, and Dietmar Maurer FPGA prototyping of a RISC Processor Core For Embedded Applications, IEEE transaction on VLSI systems, vol 9, no. 2, April (2001).

DOI: 10.1109/92.924027

Google Scholar

[2] Rainer Ohlendorf, Thomas Wild, Michael Meitinger, Holm Rauchfuss, Andreas Herkersdorf, Simulated and measured performance evaluation of RISCbased SoC platforms in network processing applications, Journal of Systems Architecture 53 , 2007, P 703–718.

DOI: 10.1016/j.sysarc.2007.01.009

Google Scholar

[3] John L. Hennessy, and David A. Patterson, Computer Architecture A Quantitative Approach, 4th Edition; (2006).

Google Scholar

[4] K. Vlachos, T. Orphanoudakis, Y. Papaeftathiou, N. Nikolaou, D. Pnevmatikatos, G. Konstantoulakis, J.A. SanchezP., Design and performance evaluation of a Programmable Packet Processing Engine (PPE) suitable for highspeed network processors units, Microprocessors and Microsystems 31, 2007, p.188.

DOI: 10.1016/j.micpro.2006.09.001

Google Scholar