CMOS Low Power Ring VCO Design

Ming Xin Song; Shan Shan Wang; Guo Dong Sun

doi:10.4028/www.scientific.net/AMR.981.70

Paper Titles

The Analysis of Institutional Factors for Gain of EDFA
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Design and Implementation of a RISC Processor on FPGA
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The Modeling of OTFT and the Measuring of Small Signal Detection Circuit
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A Bandgap Reference with Temperature Coefficient of 13.2 ppm/°C
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CMOS Low Power Ring VCO Design
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The Dual Sine Signal Generator Design Based on the Principle of Difference Frequency Filtering
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Full Scan Structure Application in the Design of 16 Bit MCU
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The Design and Verification of VGA Controller
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Particle Filter Approach for IGBT Remaining Useful Life
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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 981CMOS Low Power Ring VCO Design

CMOS Low Power Ring VCO Design

Abstract:

A design project of voltage controlled oscillator which is the central component of the low voltage phase locked loop (PLL) is proposed in this paper. The VCO adopted the folding differential voltage controlled oscillator.Simulation results in Cadence Hspice indicate that the VCO proposed behaves in good linearity, simple structure, small phase noise.The frequency range from 125 to 787 MHz, the power consumption of this oscillator is only 6mW at central frequency is 480MHz with 3V power supply.