Full Scan Structure Application in the Design of 16 Bit MCU

Hong Bo Pan; Ming Xin Song; Xing Jin; Jing Hua Yin

doi:10.4028/www.scientific.net/AMR.981.78

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HomeAdvanced Materials ResearchAdvanced Materials Research Vol. 981Full Scan Structure Application in the Design of...

Full Scan Structure Application in the Design of 16 Bit MCU

Abstract:

A design project of 16 bit RISC MCU with full scan structure by the tool of SYNOPSYSTM DFT COMPILER. The flip-flops can be linked into the chains; the memory modules in the MCU were tested by the technology of BIST; and the circuits were tested by the test vectors by ATPG. The chip test circuit include 8 chains, and cover rate can reach at 99.20%.

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Periodical:

Advanced Materials Research (Volume 981)

Pages:

78-81

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.981.78

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Online since:

July 2014

Authors:

Hong Bo Pan, Ming Xin Song*, Xing Jin, Jing Hua Yin

Keywords:

Full Scan Structure, MCU, Testability Design

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