A Novel Strategy of Area Cost Estimation for Custom Instruction Based on FPGA Architecture

Abstract:

Area cost estimation model is important for accurate measurement of area on reconfigurable processor. However, in the process of CI (Custom Instruction), traditional model can’t accurately estimate area cost of CI candidates. In the paper, we propose a novel strategy of area cost estimation. According to island-style FPGA (Field Programmable Gate Array) structure, the strategy firstly enumerated all BCs (Basic Cells) from data-path of CI candidates. Then checked all the validity of BCs enumerated, and selected the unique BC set to overlap original data-paths. We lastly used the effective estimation model based on BC to accurately measure area cost of candidates. Experimental results show that novel strategy can accurately estimate area cost of CI candidates, which is very close to actual result from a HLS (High Level Synthesis) tool, and deviation is less than 6%.

• Periodical: Advanced Materials Research (Volume 981)
• Pages: 94-98
• DOI: https://doi.org/10.4028/www.scientific.net/AMR.981.94
• Online since: July 2014
• Authors: Hai Ming Liu*, Qiang Wu
• Keywords: Area Estimation, Custom Instruction, FPGA

References

[1] K. Atasu, L. Pozzi, and P. Ienne: Automatic application-specific instruction-set extensions under microarchitectural constrains. DAC, 2003, pp.256-261.

DOI: 10.1145/775832.775897

[2] Cong J, Fan Y, Han G, and Zhang Z: Application-specific instruction generation for configurable processor architectures". FPGA, 2004, PP. 183-189.

DOI: 10.1145/968280.968307

[3] L. Pozzi, K. Atasu, and P. Ienne, Exact and approximate gorithms for the extension of embedded processor instruction sets,. IEEE Trans. on CAD of Integrated Circuits and Systems, 2006, pp.1209-1229.

DOI: 10.1109/tcad.2005.855950

[4] I-Wei Wu, Cheng-Ping Chung, Jean Jyn-Jium Shann, Area Effificent Instruction Set Extension Exploration with Hardware Design Space Exploration,. Journal of inforation science and engineering 27, 2011, pp.1641-1657.

[5] Guoqiang Liang, Yuchun Ma, Kang Zhao, Jinan Bian, Efficient Custom Instruction Generation Based on Characterizing of Basic Blocks,. 17th IEEE International Conference on Computer Supported Cooperative Work in Design, (2013).

DOI: 10.1109/cscwd.2013.6580946

[6] H. Gao, Y. Yang, X. Ma, G. Dong, Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations, in: Proceedings of the Sixth International Symposium on Quality of Electronic Design, March 2005, p.370–374.

DOI: 10.1109/isqed.2005.20

[7] http: /www. trimaran. org.