The Stress Distribution and Influence of VDMOS Device Based on ANSYS

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In this paper, the device of VDMOS packaged in a TO-220C power is acted as research object. ANSYS finite element software simulation is used to build the three dimension model, the software is also used to imitate the stress distribution under the frequency of 220Hz ~ 400Hz. The simulation result shows that the stress of the chip of corresponding to the empty space is bigger than the others as the increasing frequency on the boundary of bonding layer and the chip, which easily leads to micro deformation of the bonding layer and the micro crack of the chip. The value of stress effects by changing the bonding layer material and layer thickness, the simulation results show that the bigger heat conductivity coefficient and the thinner thickness of bonding layer is the smaller stress, Which the design of the bonding layer can be optimized. The results of the study provide the theoretical basis for the structural design of the device, founding the weakness of structure design, having guiding significance for improving the reliability of the device.

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936-939

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July 2014

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© 2014 Trans Tech Publications Ltd. All Rights Reserved

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