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FIR Sine Interpolation Algorithm Based on Pipeline and Parallel Technology
Abstract:
According to the problem that the existing data interpolation algorithm has low efficiency when handling high-speed data, this paper proposes a FPGA-based FIR sine interpolation algorithm based on pipeline and parallel technology. The algorithm not only reduces the critical path so that improve the system working clock effectively, but also increases the speed of data processing to improve the speed of interpolation process significantly. Finally, according to the experiment based on FPGA, the result shows that the proposed algorithm improves the speed of data interpolation process, and reduces the system power consumption effectively. It can realize the real-time interpolation process of high-speed or hyper-speed data stream.
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1422-1425
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Online since:
July 2014
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© 2014 Trans Tech Publications Ltd. All Rights Reserved
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