Improved XFBT: A Low-Power Topology of Network-on-Chip

Hong Bing Chen; Chao Li

doi:10.4028/www.scientific.net/AMR.989-994.4865

Paper Titles

Topic-Oriented Information Retrieval
p.4845

Representing and Preparing for Resources in EPM’s Execution Model
p.4851

Application of Gis in Environmental Impact Assessment
p.4855

Remote Maintenance System Based on Browser\Server and VIRTOOLS
p.4861

Improved XFBT: A Low-Power Topology of Network-on-Chip
p.4865

A Database Grid Service with a Novel Mutation Operator
p.4869

Research on Algorithm to Improve Performance of Wireless-Optical Broadband Access Network
p.4873

Research on Image Vectorization Based on Fuzzy Neural Network and Expert System
p.4877

Research on Social Engineering in Network Security
p.4881

HomeAdvanced Materials ResearchAdvanced Materials Research Vols. 989-994Improved XFBT: A Low-Power Topology of...

Improved XFBT: A Low-Power Topology of Network-on-Chip

Abstract:

The article discusses the issues related to the on-chip network topology, analyzes the XBFT topology, improves its structure in power consumption. Authors designed a simulation program that by analyzing the topology routing hops to roughly determine the power consumption of routing topology and for the preparation of modified XBFT roughly determine the topology of the routing topology by analyzing the power consumption topology routing hops the simulation program, Finally, the results from the running of 6 simulation program that extracted and these results were analyzed. The result shows that the improved topology saved about 20% of the number of routing hops.

You might also be interested in these eBooks

View Preview

Info:

Periodical:

Advanced Materials Research (Volumes 989-994)

Pages:

4865-4868

DOI:

https://doi.org/10.4028/www.scientific.net/AMR.989-994.4865

Citation:

Cite this paper

Online since:

July 2014

Authors:

Hong Bing Chen*, Chao Li

Keywords:

Improved XFBT, Low-Power, NoC, Topology

Export:

RIS, BibTeX

Price:

Permissions CCC:

Request Permissions

Permissions PLS:

Request Permissions

Сopyright:

Citation:

* - Corresponding Author

References

[1] D. Heckerman, C. Meek, and G. Cooper. A Bayesian approach to causal discovery. In C. Glymour and G. F. Cooper, editors, Computation, Causation, and Discovery, pages 141–166. MIT Press, (1999).

Google Scholar

[2] T. Richardson and P. Spirtes. Automated discovery of linear feedback models. In C. Glymour and G. F. Cooper, editors, Computation, Causation, and Discovery, pages 253–304. MIT Press, (1999).

DOI: 10.7551/mitpress/2006.003.0014

Google Scholar

[3] R. Silva, R. Scheines, C. Glymour, and P. Spirtes. Learning the structure of linear latent variable models. Journal of Machine Learning Research, 7: 191–246, (2006).

Google Scholar

[4] S. Kumar et al., A Network on Chip Architecture and esign Methodology, Proc. Int'1 Symp. VLSI(ISVLSI), pp.117-124, (2002).

Google Scholar

[5] W.J. Dally and B. Towles, Route Packets, Not Wires: On-Chip Interconnection Networks, Proc. Design Automation Conf. (DAC), pp.683-689, (2001).

DOI: 10.1145/378239.379048

Google Scholar

[6] F．Karim et a1, An Interconnect Architecture for Networking Systems on Chips[C]. IEEE Micro，vo1. 22，no. 5，pp.36-45，Oct, 2002.

Google Scholar

[7] WANG Ji-He, GUO Bing, etc. Analysis and Modeling of Directory Protocol Energy Consumption in NoC[J]. Chinese Journal of Computers, 2011, 34(9): 1603-1610.

DOI: 10.3724/sp.j.1016.2011.01603

Google Scholar