A Promising Hardware Accelerator with PAST Adder

Abstract:

Recent neural network research has demonstrated a significant benefit in machine learning compared to conventional algorithms based on handcrafted models and features. In regions such as video, speech and image recognition, the neural network is now widely adopted. But the high complexity of neural network inference in computation and storage poses great differences on its application. These networks are computer-intensive algorithms that currently require the execution of dedicated hardware. In this case, we point out the difficulty of Adders (MOAs) and their high-resource utilization in a CNN implementation of FPGA .to address these challenge a parallel self-time adder is implemented which mainly aims at minimizing the amount of transistors and estimating different factors for PASTA, i.e. field, power, delay.

• Periodical: Advances in Science and Technology (Volume 105)
• Pages: 241-248
• DOI: https://doi.org/10.4028/www.scientific.net/AST.105.241
• Online since: April 2021
• Authors: Abhishek Choubey*, Shruti Bhargava Choubey
• Keywords: CNN, DLHA, Hardware Accelerator

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